Hitachi AP1 Data Book page 257

------------------------------------------------------------------HMCS404C
Table 27. Compare Instruction
~
OPERATION MNEMONIC
OPERATION CODE FUNCTION STATUS
YCLE
Immediate Not Equal to Memory INEM
i
o
0 0 0 1 0 iJ i2
i,
io i 10M NZ 1/1
Immediate Not Equal to Memory INEMD i.d
~ ~8~7~.JS~'~ ~ ~,~
i iM NZ 2/2
A Not Equal to Memory
ANEM 0000000100 A",M NZ 1/1
A Not Equal to Memory
ANEMD d
~gJa~7~6~5~.~3J2~' ~o
AIM
NZ
2/2
B Not Equal to Memory BNEM 0001000100 B/M NZ 1/1
Y Not Equal to Immediate
YNEI
I
00011 1 iJ b i, io Yi-i NZ 1/1
Immediate Less or Equal to Memory
ILEM i 00001 1
iJ h
i, io i ~M NB 1/1
Immediate Less or Equal to Memory
ILEMD
i.d
~9J8~7~.J5J.~ ~,~\ ~
i ~M NB
2/2
A Less or Equal to Memory ALEM 0000010100 A~M NB 1/1
- - - - - - - - - - - - - - - - - - - -
0100010100
A Less or Equal to Memory ALEMD d
dg da d7 d6 d5 d. d3
~Q
A~M NB 2/2
- - - - - - - - - - - - - - - - - - - - - - - - - -
B Less or Equal to Memory BLEM
0011000100 B~M NB
1/1
- - - -
A Less or Equal to Immediate ALE I i 1 0 1 0 1 1 iJ i2 i, io A~ i NB
1/1
Table 28. RAM Bit Manipulation Instruction
OPERATION
MNEMONIC OPERATION CODE FUNCTION
2
STATUS
CYCL
Set Memory Bit
SEM n
00 1 0000 1 n,no 1--M(n) 1/1
Set Memory Bit SEMD n.d
01 1 00001 n,no
dg ded7 d6 d5 d. d3 d2 d, do
1--+M(n)
2/2
Reset Memory Bit REM n
001 000 1 0 n,no O--+M(n)
1/1
Reset Memory Bit REMD n.d
o
1 1 00
U.
1
U.
n,no
dg d8 d7 d6 d5 d. d3 d2 d, do
O--+M(n)
2/2
Test Memory Bit TM n
001 0001 1 n,no M(n)
1/1
Test Memory Bit
TMD n.d
q
1 1 000 1 1 n,no
dg da d7 d6 ds d. d3 d2 d, do
M(n)
2/2
Table
29. ROM
Address Instruction
I
MNEMONIC
~
OPERATION OPERATION CODE FUNCTION STATUS
CYCL
Branch on Status 1 BR b 1 1 b7b6b5b4bJb2b,bo
1
1/1
Long Branch on Status 1 BRL u
o
1 0 1 1 1 PJP2P,PO
1
2/2
dg da d7 d6 d5 d. d3 d2 d, do
Long Jump Unconditionally
JMPL u
o
1 0 1 0 1 PJP2P'PO
dgdsd7d6d5d.d3d2d, do
2/2
Subroutine Jump on Status 1
CAL a
o
1 1 1 a5a4aJa2a,aO 1 1/2
Long Subroutine Jump on Status 1 CALL u
~g
Js
~7
J6 J5
~4 ~~:~,'~g
1 2/2
Table Branch TBR
P
o
0 1 0 1 1 PJP2P,PO 1/1
Return from Subroutine RTN 0000010000
1/3
Return from Interrupt RTNI 0000010001
l--+I/E 1/3
Table
30.
Input/Output Instruction
OPERATION
MNEMONIC OPERATION CODE
~
FUNCTION
STATUS
YCLE
Set Discrete I/O Latch SED
o
0 1 1 1 0 0 1 0 0 1--+D(Y)
1/1
Set Discrete I/O Latch Direct SEDD m 1 0 1 1 1 0 m3m2m,mO
l--+D(m)
1/1
Reset Discrete I/O Latch RED
o
0 0 1 1 0 0 1 0 0 O--+D(Y)
1/1
Reset Discrete I/O Latch Direct REDD m 1
o
0 1 1 0 mJm2m,mO O--+D(m)
1/1
Test Discrete I/O Latch TD
o
0 1 1 1
o
0 000 D(Y)
1/1
Test Discrete I/O Latch Direct
TDD m 1 0 1 0 1 0 m3m2m,mO
D(m)
1/1
load A from R-Port Register
LAR m 1
o
0 1 0 1 m3m2m,mO R(m)--+A
1/1
Load B from R-Port Register
LBR m 1
o
0 1
o
0 mJm2m,mO R(m)--+B
1/1
Load R-Port Register from A lRA m
1 0 1 1
o
1 m3m2m,mO A--+R(m)
1/1
load R-Port Register from B LRB m 1 0 1 1
o
0 m3m2m,mO B--+R(m)
1/1
Pattern Generation
P
P
o
1 1 0 1 1 P3P2P, Po
1/2
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