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CN1
IC1
PLL+IN
3
14
+
1
DR, 5-14
PLL_IN
2
_
DR, 5-13
13
IC3
1
4
CN1
SYNC 59 ON IN
DR, 5-20
20
OBLK1
DR, 5-16
16
OBLK2
DR, 5-15
15
SLOW SCAN IN
DR, 5-18
18
CN1
+5.5 V
DR, 5-5, 6
5, 6
CN2
+5.5 V
NR
19, 20
IC5
REF. V
CN1
_5.5 V
DR, 5-4
4
CN2
_5.5 V
NR
21
CN1
OPB PLS
DR, 5-7
7
VL IN
DR, 5-3
3
TG-209
TG-209
Block Diagram
Block Diagram
+5 V
Q6
IC6
CP2
4
1
74.25
3
13
CLK60
MHz
+5 V
IC4
2
4
Q3
CP1
4
1
74.1875
3
14
CLK59
MHz
MPX1/XST5
MPX2/XST6
21
CLK59/60/S-CLK
8
BLK1/S-DATA
10
BLK2/S-LD
RPCLK/XST3
41
SSNORM
IC1, Q1, 2
TIMING GENERATOR
+5 V
+5 V
REG.
IC2, Q4, 5
+3.3 V
+3.3 V
REG.
_5.5 V
6-4
6-4
IC8
51
2
6
XLH1 OUT
XLH/XIM1
IC7
48
2
4
XRG OUT
XRG/XIM4
50
XH1 OUT
XH1/XIM2
49
XH2 OUT
XH2/XIM3
58
MPX-1 OUT
57
MPX-2 OUT
59
SHP
XSH/XST4
62
RPCLK
64
HCLK
37P/XST1
+3.3 V
Q9, 10
+37M OUT
AMP
_5.5 V
+3.3 V
Q7, 8
_37M OUT
63
37N/XST2
AMP
_5.5 V
SLOW SCAN ON
CLP
VL OUT
CN1
23
DR, 5-23
CN1
21
DR, 5-21
CN1
17
DR, 5-17
19
DR, 5-19
CN2
11
NR
13
NR
3, 4
NR
CN1
8
DR, 5-8
9, 10
DR, 5-9, 10
CN1
12
DR, 5-12
CN1
11
DR, 5-11
CN2
7
NR
CN2
6
NR
22
NR
TG-209
HKC-7080
HDC700A-TG209-BLOCK/M
HKC-7080
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