Siemens C16 Series Instruction Set Manual page 127

• Jumps into the internal ROM space: T Iadd = 0 or 2
The minimum time of 4 state times for standard jumps into the internal ROM space will be extended
by 2 additional state times, if the branch target instruction is a double word instruction at a non-
aligned double word location (xxx2
label : ....
.... : ....
I n+1 : JMPA cc
A cache jump, which normally requires just 2 state times, will be extended by 2 additional state
times, if both the cached jump target instruction and its successor instruction are non-aligned
double word instructions, as shown in the following example:
label : ....
I t+1 ....
:
I n+1 :JMPR cc
If required, these extra state times can be avoided by allocating double word jump target
instructions to aligned double word addresses (xxx0
• Testing Branch Conditions: T
Mostly, NO extra time is required for conditional branch instructions to decide whether a branch
condition is met or not. However, an additional state time is required, if the preceding instruction
writes to the PSW register, as shown in the following example:
I n : BSET USR0
I n+1 :JMPR cc
In this case, the extra state time can simply be intercepted by putting another suitable instruction
before the conditional branch instruction.
Semiconductor Group
30Mar98@15:00h
, xxx6
H
; any non-aligned double word instruction
: (eg. at location 0FFE
_
UC, label ; if a standard branch is taken:
: T Iadd = 2
; any non-aligned double word instruction
: (eg. at location 12FA
; any non-aligned double word instruction
: (eg. at location 12FE
_
UC, label ; provided that a cache jump is taken:
: T Iadd = 2
= 0 or 1
Iadd
; write to PSW
_
Z, label ; test condition flag in PSW: T Iadd = 1
C166 Family Instruction Set
States
*
, xxxA , xxxE ), as shown in the following example:
H H H
)
H
States (T In = 6
*
)
H
)
H
States (T In = 4
*
, xxx4 , xxx8
H H
States
*
127
Instruction State Times
States)
*
States)
*
, xxxC ).
H H
State
*
Version 1.2, 12.97