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DIVU
Syntax
Operation
Data Types
Description
Condition Flags
Addressing Modes
Semiconductor Group
30Mar98@15:00h
16-by-16 Unsigned Division
DIVU
op1
(MDL) ← (MDL) / (op1)
(MDH) ← (MDL) mod (op1)
WORD
Performs an unsigned 16-bit by 16-bit division of the low order word
stored in the MD register by the source word operand op1. The signed
quotient is then stored in the low order word of the MD register (MDL) and
the remainder is stored in the high order word of the MD register ( MDH).
E
Z
0
*
E Always cleared.
Z Set if result equals zero. Cleared otherwise.
V Set if an arithmetic overflow occurred, ie. the result cannot be repre-
sented in a word data type, or if the divisor (op1) was zero. Cleared
otherwise.
C Always cleared.
N Set if the most significant bit of the result is set. Cleared otherwise.
Mnemonic
DIVU
Rw
n
C166 Family Instruction Set
V
C
N
S
0
*
Format
5B nn
66
Instruction Description
DIVU
Version 1.2, 12.97
Bytes
2
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