Sanyo VM-EX70P Adjustment Manual page 40

2-6. IC91 5 (CXD1 159Q)
Pin @ of IC91 5 (CXD1 1 59Q) receives the 1 4 MHz clock
from Pin @ of IC91 6 (CXD1 256R) and generates various
sync signals. The block diagram, timing chart and pin
functions are shown in Fig. 2-1 3, 2-1 4 and 2-1 5 and Table
2 - 4 respectively.
FSC1
FSCO
C LK1
C LKO
CXD1 1 59Q
>
1 /4
1 / 5
1 /4
IC915
iii
Fig. 2-13. IC91 5 Block Diagram
1 /227
1/65
H-DECODER
0
0
()
�
Cl
Cl
z
>
:::c
- 4 - 1 8 -
PHASE
COM PARATOR
g
UJ Cl
�
Cl z
u.
�
z
COM P
P SEL
MODE
TEST
EXT
HR
VR
LR
V I NT