Sharp SL-5500 Service Manual page 10

Name Type
nRESET_OUT OCZ
nTRST IC
TDI IC
TDO OCZ
TMS IC
TCK IC
TCK_BYP IC
TESTCLK IC
VDD –
VDDX –
VSS –
VSSX –
2-2. ANALOG FRONT END LSI (TC35143AF)
(1) OUTLINE
TC35143AF is an analog front end LSI suitable for personal digital
assistants (PDA) including HPC. It consists of a V.34 modem tele-phone
line interface, sound interface compatible with the handsfree / handset
system, and touch screen interface. The communication with the host
processor is performed through the SIB (Serial Interface Bus). The LSI
is connectable to a master processor with an SIB interface. Clocks used
inside the TC35143AF are generated from the serial transfer clocks of
the SIB interface. There is no need for any clock oscillator. Sampling
data, control signals and status of each interface block is communicated
with the host processor through the SIB interface.
(2) FEATURES
(2)-1. TELEPHONE LINE INTERFACE
• 16-bit ADC/DAC
• Programmable input amplifier gain (2-stage, in steps of 6dB)
• Full differential telephone line interface
• Analog echo canceller is incorporated
• Programmable sampling frequency (3-stage : 7.2 kHz, 8 kHz, 9.6
kHz)
(2)-2. SOUND INTERFACE
• 14-bit ADC/DAC
• 2 mike input lines, 2 speaker output lines (supports handsfree, hand-
set system)
• Power On/Off function for each block
• Mike input mute switch, speaker input mute switch
• Programmable mike amplifier gain (2 types: 15 stages in steps of
1.5dB and 4 stages in steps of 6dB)
• Programmable speaker output level attenuator (8 stages in steps of
3dB)
• Programmable sampling frequency (4 stages in steps of 8 kHz, about
11.03 kHz, 16 kHz, about 22.05 kHz)
Reset out. This signal is asserted when nRESET is asserted and deasserts when the processor has com-
pleted resetting. nRESET_OUT is also asserted for "soft" reset events (sleep and watchdog).
Test interface reset. Note this pin has an internal pull-down resistor and must be driven high to enable the
JTAG circuitry. If left unconnected, this pin is pulled low and disables JTAG operation.
JTAG test interface data input. Note this pin has an internal pull-up resistor.
JTAG test interface data output. Note this pin does not have an internal pull-up resistor.
JTAG test interface mode select. Note this pin has an internal pull-up resistor.
JTAG test interface reference clock. This times all the transfers on the JTAG test interface. Note this pin
has an internal pull-down resistor.
Test clock PLL bypass. When TCK_BYP is high, the TESTCLK is used as the core clock in place of the
PLL clock; when low, the internal PLL output is used. This signal has no relation to the JTAG TCK pin.
Test clock . TESTCLK is used to provide the core clock when TCK_BYP is high. It should be tied low if
TCK_BYP is low. This pin should be used for test purposes only. An end user should ground this pin.
Positive supply for the core. Nine pins are allocated to this supply; eight pins are labeled VDD. The ninth
pin, labeled VDDP is dedicated to the PLL supply and should have its own dedicated decoupling capaci-
tor. Also, it should be tied directly to the VDD power plane with the other eight VDD pins.
Positive supply for the pins. For a count of VDDX pins. All of the pins allocated to VDDX (labeled VDDX1,
VDDX2, and VDDX3) should be tied directly to the VDDX power plane. VDDX3 should have its own dedi-
cated decoupling capacitor.
Ground supply. Nine pins are allocated to VSS, including one for the PLL.
Ground supply for the I/O pins. "Package and Pinout", for a count of VSSX pins.
SL-5500 HARDWARE DESCRIPTION
– 9 –
Description
(2)-3. TOUCH SCREEN INTERFACE
• Voltage measurement 10-bit ADC
• Touch starting mode from stand-by state
• Plate applied voltage generation circuit
• General-purpose analog input port (4 inputs)
(2)-4. OTHERS
• Interrupt output port (programmable interrupt factor setting function)
• Multichip connection through SIB interface (SIB clock input fixed to
9.216 MHz)
• General-purpose I/O port (10 ch)
• +3.3V battery power supply
• 64-pin QFP package
(3) SYSTEM BLOCK DIAGRAM
SCLK
SDOUT
SIB master
SDIN
processor
SSYNC
IRQ
Data Bus
Flash
RAM
ROM
PC-UM10M
Tou ch
Battery
Screen
3.3V
TC35143F
M
NCU
Peripheral