Sharp SL-5500 Service Manual page 23

PC-UM10M
(2) PIN LAYOUT
5O 5O 5O 5O
GND 107
5O CA23 110
5O CA12
5O CA24
5O CA7
5O CA25
TQFP144pins (126 user pins and 18 power supply pins)
5O CA6 115
5O CA5
HVDD
VDD=3.3V (fixed power supply)
5O CRESET
HVDD=5.0/3.3/0V (Variable)
5O CA4
5I CWAIT_B 120
5O CA3
5O CA2
5O CREG_B
5O CA1
5I CBVD2 125 Buffer type
5O CA0
Example: 3IS(Special)
5I CBVD1
HVDD
5IO CD0
5IO CD8 130
5IO CD1
5IO CD9
5IO CD2
5IO CD10
The shaded items show card pins which
5I CIOIS16_B 135
GND
require an external pull-up resistance.
LVDD
3I CCD1_B
3I CCD2_B
Pin arrangement used when
3I S CVS1_B 140
CREV pin is fixed to Lo.
3I S CVS2_B
3O CVCCDOWN_B
3O CVCC3EN_B 143
3O CVCC5EN_B 2
3O 3O 3I 3I
(3) COMPACT FLASH MODE
(GENERAL-PURPOSE I/O TERMINAL)
Since the dedicated Compact Flash mode does not need address lines
PA11 - PA22 and CA11 - CA25, they can be used for other purposes.
However, it is difficult to use CA11 - CA25 because the card power sup-
ply might be turned off. PA11 -PA22 can easily used because LVDD is
fixed to 3.3V.
(3)-1. GPIO PINS (PA11 - PA19)
For this reason, pins PA11 to PA19 can be used as general-purpose I/
Os according to the setting in the CF mode.
Note: 1. In the CF mode, the above address bus pins are automati-
cally pulled down if set to the GPIO input mode (initial
value). The pull-down resistance value is 40k-240kΩ
(TYP100kΩ)
2. These pins are basically used for address bus input, and
thus input is not Schmitt received.
5I 5O 5O 5O 5O 5O 5O 5O 5O 5O
100 95
Buffer with pull-up/pull-down resistance control function
I=Input buffer, O= Output buffer, IO=I/O buffer
VDD (3=3.3V fixed [LVDD], 5=5/3.3/0V variable [HVDD]
10 15
3IO 3IO 3IO 3IO 3IO 3IO 3IO 3IO 3IO 3IO
SL-5500 HARDWARE DESCRIPTION
5O 5O 5O 5O 5O 5O 5IO 5O 5IO 5IO
90 85
Scoop ASIC
20 25
3IO 3IO 3IO 3IO 3IO 3IO 3I 3I 3I 3IO
(3)-2. GLUE-LOGIC PINS
[PA20, PA21: INPUT, PA22: OUTPUT]
The following logic (DFFx1) is connected to solve the problem with the
signal phase relationship between the panel controller and CPU
(SA1110).
Circuit diagram
PA21
L-LCLK
L-PCLK
PA20
SA1110 (CPU)
– 22 –
5IO 5IO 5IO 5IO 5IO 5IO 5IO
80 75 74 TEST
71 RESET_B
70 PCE1_B
IOIS16_B
PREG_B
PCE2_B
PWAIT_B
65 POE_B
PIOR_B
LVDD
PWE_B
PIOW_B
60 CS4_B
OE_B
WE_B
PIRQ_B
PRDY
55 PSKTSEL
PSKTSEL2
GND
PA0
PA1
50 PA2
PA3
PA4
PA5
PA6
45 PA7
LVDD
PA8
PA9
PA10
40 PA11
PA12
38 PA13
30 35 GND
3I 3I 3I S 3I S 3I S 3I S 3I S 3I S
HS_OUT
HS
DFF
PA22
RESET_B
Scoop (CF card mode.)
3I
3I
3I
3O
3I
3I
3O
3I
3I
3I
3I
3I
3I
3I
3O
3O
3I
3I
3I
3I
3I
3I
3I
3I
3I
3I
3I
3I
3I
3I S
3I S
3I S
Buffer type
Panel controller