Sharp SL-5500 Service Manual page 8

(4) SIGNAL DESCRIPTION
The following table describes the signals.
Key to Signal Types: n:Active low signal
IC:Input, CMOS threshold
ICOCZ:Input, CMOS threshold, output CMOS levels, tristatable
OCZ:Output, CMOS levels, tristatable
(4)-1. SIGNAL DESCRIPTION
Name Type
A 25:0 OCZ
D 31:0 ICOCZ
nCS 5:0 OCZ
RDY IC
nOE OCZ
nWE OCZ
nRAS 3:0/nSDCS 3:0 OCZ
nCAS 3:0/DQM 3:0 OCZ
nSDRAS OCZ
nSDCAS OCZ
SDCKE 1:0 OCZ
CDCLK 2:0 OCZ
RD/nWR OCZ
nPOE OCZ
nPWE OCZ
Memory address bus. This bus signals the address requested for memory accesses.
Bits 24..10 carry the 15-bit DRAM address. The static memory devices and the expansion bus receive
address bits 25..0.
Memory data bus. Bits 15..0 are used for 16-bit data busses.
Static chip selects. These signals are chip selects to static memory devices such as ROM and Flash.
They are Individually programmable in the memory configuration registers. Bits 5..3 can be used with vari-
able latency I/O devices.
Static data ready signal for nCS 5:3. This signal should be connected to the data ready output pins of vari-
able latency I/O devices that require variable data latencies. Devices selected by nCS 5:3 can share the
RDY pin if they drive it high prior to tristating and a weak external pull-up is present.
Memory output enable. This signal should be connected to the output enables of memory devices to con-
trol their data bus drivers.
Memory write enable. This signal should be connected to the write enables of memory devices. This sig-
nal is used in conjunction with nCAS 3:0 to perform byte writes.
DRAM RAS or SDRAM CS for banks 0 through 3. These signals should be connected to the row address
strobe (RAS) pins for asynchronous DRAM or the chip select (CS) pins for SDRAM.
DRAM CAS or SDRAM DQM for data banks 0 through 3. These signals should be connected to the col-
umn address strobe (CAS) pins for asynchronous DRAM or the data output mask enables (DQM) for
SDRAM.
SDRAM RAS. This signal should be connected to the row address strobe (RAS) pins for all banks of
SDRAM.
SDRAM CAS. This signal should be connected to the column address strobe (CAS) pins for all banks of
SDRAM.
SDRAM and/or SMROM clock enables.
SDCKE 0 should be connected to the clock enable (CKE) pins of SMROM.
SDCKE 0 is asserted upon any rest (including sleep-exit) if static memory bank 0 (boot space) is config-
ured for synchronous mask ROM (SMROM_EN = 1);otherwise it is deasserted upon reset.
SDCKE 1 should be connected to the clock enable pins of SDRAM. They are deasserted (held low) during
sleep. SDCKE 1 always is deasserted upon reset.
The memory controller provides control register bits for deassertion of each SDCKE pin. However,
SDCKE 0 cannot be deasserted via program if SMROM_EN = 1.
SDRAM and/or SMROM clock.
SDCLK 0 should be connected to the clock (CLK) pins of SMROM.
SDCLK 1 and SDCLK 2 should be connected to the clock pins of SDRAM in bank pairs 0/1 and 2/3,
respectively. They are driven by either the internal memory controller clock (CPU clock divided by 2) or the
memory controller clock divided by 2 (CPU clock divided by 4).
All SDCLK pins are held low during sleep mode and start running at CPU clock divide by 4 upon any reset
(including sleep-exit).
The memory controller provides control register bits for clock division and disable of each SDCLK pin.
However, SDCLK 0 cannot be disabled via program if static memory bank 0 (boot space) is configured for
synchronous mask ROM (SMROM_EN = 1).
Read/write direction control for memory and PCMCIA data bus (D 31:0). This signal is applicable to all
memory bus and PCMCIA transfers.
For reads (RD/nWR = 1), system-level bus transceivers or directly connected memory devices should
drive D 31:0.
For writes (RD/nWR = 0), the SA-1110 will drive D 31:0.
PCMCIA output enable. This signal is an output and is used to perform reads from memory and attribute
space.
PCMCIA write enable. This signal is an output and is used to perform writes to memory and attribute
space.
SL-5500 HARDWARE DESCRIPTION
– 7 –
Description
PC-UM10M