Sharp SL-5500 Service Manual page 14

(2) PIN CONFIGURATION
A15 1
A14 2
A13 3
A12 4
A11 5
A10 6
A9 7
A8 8
A21 9
A20 10
48-LEAD TSOP
WE# 11
STANDARD PINOUT
RST# 12
VPP 13 12mm x 20mm
WP# 14
TOP VIEW
A19 15
A18 16
A17 17
A7 18
A6 19
A5 20
A4 21
A3 22
A2 23
A1 24
(3) PIN NAMES
Symbol Type
A0-A21 Input Address input: Address input pin 64M: A0-
A21
DQ0-DQ15 Input/ Data I/O: This pin outputs data that is writ-
Output ten to CUI (Command User Interface), com-
mand input, memory array, status register,
query code, ID code, and device configura-
tion code read data. When the chip is not
selected or output is disabled, the pin is at
high impedance (High Z). Data is erased or
latched internally while a program is run-
ning.
CE# Input Chip enable: This pin activates device con-
trol logic, input buffer, decoder and sense
amplifier. When CE# is VIH, device is not
selected and power turns to stand-by level.
RST# Input Reset: When RST# is VIL, the inside of
device is automatically reset to prohibit era-
sure and running of the program, thus pro-
tecting data. When RST# is VIH, device is
set to usual operation mode.
After power is turned on, or after power is
restored from the reset mode, device is
automatically set to a synchronous array
read mode.
when power is turned on, RST# needs to be
set to VIL.
OE# Input Output enable: This pin controls the output
terminal of device in reading.
WE# Input Write enable: This pin controls writing to
CUI and memory array. The address and
data are latched at the leading edge of CE#
or WE# whichever comes first.
WP# Input W rite protect : W hen WP # is VIL, T he
release of lock bit in the block to which lock-
down bit is set is prohibited. For blocks to
which either lock bit or lock-down bit is not
set, erasure or program operation can be
performed. Lock-down bit can be disabled
by putting WP# in VIH.
48 A16
47 VCCQ
46 GND
45 DQ15
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 GND
26 CE#
25 A0
Name and function
SL-5500 HARDWARE DESCRIPTION
– 13 –
Symbol Type
VPP Input Power supply voltage detection pin: VPP is
not a power supply pin. When VPP VPPLK,
it is not possible to execute block erasure,
full-chip erasure, (page buffer) program or
OTP program. Do not try to execute such
operations.
High-speed erasure and high-speed pro-
gram operation can be executed by apply-
ing a voltage of 12V m 0.3 V to VPP, and at
this time, VPP acts as a power supply pin.
If VPP voltage is used at 12V m 0.3V during
erasure or the running of a program, the
number of rewrites per block is up to 1000.
If 12V m 0.3V is applied to VPP pin, it is
required to set up to 80 hours in accumula-
tion. If more than 12V is applied to VPP,
there is a possibility of reducing the number
of rewrites or irreversible destruction.
VCC Supply Device power supply (see delivery specifi-
cation): When VCCVLKO, writing to flash
memory is prohibited. If the system is used
at an invalid VCC voltage (see DC charac-
teristics), malfunction might result. Do not
use the system at such a state.
VCCQ Supply I/O power supply (see delivery specifica-
tion); Power supply for I/O pin
GND Supply Ground: All ground pins need to be con-
nected.
NC This pin is not connected to the internal cir-
cuit. It may be used in open state.
2-5. GATE ARRAY SPECIFICATION
(1) GENERAL DESCRIPTION
The LOCOMO-QFP15-128pin G/A (SLA5075H) is a gate array devel-
oped for the SL-5500.
The outlines of built-in functions are described below.
(2) FUNCTION DESCRIPTION
(2)-1. BOOT SWITCHING, MCS DECODER [memc]
(2)-1-1. Outline
This module divides the area of chip select signal connected to cs0_b
and cs1_b pins into mos00_b, mos01_b, mos02_b, mos03_b, mos10_b,
mos11_b, mos12_b, and mos13_b according to the capacity of memory
to be connected.
In addition, the module detects the connection of FROM with from_b. If
FROM is inserted, os0_b is replaced with os1_b and decoded to start
from memory connected to os1_b.
This module is not affected by the state of pwren or battfault.
(2)-1-2. Block diagram
Here is a block diagram of this module.
CPU bus
mcsx[1:3]
from_b
Decoder
cs0_b,cs1_b
adr[25:23]
PC-UM10M
Name and function
memc
Register
mcsx0
mcs*0_b
Decoder
mcs*1_b
mcs*2_b
mcs*3_b