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5.13 Supply Voltage Detection
(SVD) Circuit
5.13.1 Configuration of SVD circuit
The E0C88832/88862 has a built-in supply voltage
detection (SVD) circuit configured with a 4-bit
successive approximation A/D converter.
The SVD circuit has 16 sampling levels (level 0–
level 15) for supply voltage, and this can be control-
led by software.
In addition, an initial reset signal can be generated
when the supply voltage drops to level 0 or less.
This is selected by the mask option.
Figure 5.13.1.1 shows the configuration of the SVD
circuit.
5.13.2 Operation of SVD circuit
Sampling control of the SVD circuit
The SVD circuit has two operation modes: continu-
ous sampling and 1/4 Hz auto-sampling mode.
Operation mode selection is done by the SVD control
registers SVDON and SVDSP as shown in Table
5.13.2.1. When both bits of SVDON and SVDSP are
set to "1", continuous sampling is selected.
Table 5.13.2.1 Correspondence between control register
and operation mode
SVDON
SVDSP
0
0
0
1
×
1
Other reset factor
OSC1
oscillation
circuit
E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit)
Operating mode
SVD circuit OFF
1/4 Hz auto-sampling ON
Continuous sampling ON
V
DD
Reference voltage
generation circuit
2,048 Hz
f
Dividing
OSC1
circuit
1/4 Hz
Fig. 5.13.1.1 Configuration of SVD circuit
In both operation modes, reading SVDON can
confirm whether the SVD circuit is operating
(BUSY) or on standby (READY); "1" indicates BUSY
and "0" indicates READY.
When executing an SLP instruction while the SVD
circuit is operating, the stop operation of the OSC1
oscillation circuit is kept waiting until the sampling
is completed. The two bits of SVDON and SVDSP
are automatically reset to "0" by hardware while
waiting for completion of sampling.
To reduce current consumption, turn the SVD
circuit OFF when it is not necessary.
Detection result
The SVD circuit A/D converts the supply voltage
(V
–V
) by 4-bit resolution and sets the result
DD
SS
thereof into the SVD0–SVD3 register.
The data in SVD0–SVD3 correspond to the detec-
tion levels as shown in Table 5.13.2.2 and the
detection data is maintained until the next sam-
pling.
For the correspondence between the detection level
and the supply voltage, see "7 ELECTRICAL
CHARACTERISTICS".
An interval of 7.8 msec (f
required from the start of supply voltage sampling
by the SVD circuit to completion by writing the
result into SVD0–SVD3. Therefore, when reading
SVD0–SVD3 before sampling is finished, the
previous result will be read.
Initial
reset
circuit
Mask option
4-bit A/D
converter
Sampling
SVDON
control
SVDSP
circuit
EPSON
= 32.768 kHz) is
OSC1
Internal initial reset
SVD3
SVD2
SVD1
SVD0
109
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