Watchdog Timer; Configuration Of Watchdog Timer; Interrupt Function; Control Of Watchdog Timer - Epson 0C88832 Technical Manual

5.2 Watchdog Timer

5.2.1 Configuration of watchdog timer

The E0C88832/88862 is equipped with a watchdog
timer driven by OSC1 as source oscillation. The
watchdog timer must be reset periodically in
software, and if reset of more than 3–4 seconds
(when f = 32.768 kHz) does not take place, a
OSC1
non-maskable interrupt signal is generated and
output to the CPU.
Figure 5.2.1.1 is a block diagram of the watchdog
f 1 Hz
OSC1
OSC1
oscillation Divider
circuit
WDRST
Watchdog timer
reset signal
timer.
Fig. 5.2.1.1 Block diagram of watchdog timer
By running watchdog timer reset during the main
routine of the program, it is possible to detect
program runaway as if watchdog timer processing
had not been applied. Normally, this routine is
integrated at points that are regularly being
processed.
The watchdog timer continues to operate during
HALT and when a HALT state is continuous for
longer than 3–4 seconds, the CPU shifts to excep-
tion processing.
During SLEEP, the watchdog timer is stopped.
Address Bit Name
00FF40 D7 –
–
D6 FOUT2
FOUT frequency selection
D5 FOUT1
D4 FOUT0
D3 FOUTON
FOUT output control
D2 WDRST Watchdog timer reset
D1 TMRST
Clock timer reset
D0 TMRUN Clock timer Run/Stop control
E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer)
Watchdog
Non-maskable
interrupt (NMI)
timer
Table 5.2.3.1 Watchdog timer control bits
Function
FOUT2 FOUT1 FOUT0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

5.2.2 Interrupt function

In cases where the watchdog timer is not periodi-
cally reset in software, the watchdog timer outputs
an interrupt signal to the CPU's NMI (level 4) input.
Unmaskable and taking priority over other inter-
rupts, this interrupt triggers the generation of
exception processing. See the "E0C88 Core CPU
Manual" for more details on NMI exception
processing.
This exception processing vector is set at 000004H.

5.2.3 Control of watchdog timer

Table 5.2.3.1 shows the control bits for the watch-
dog timer.
WDRST: 00FF40H•D2
Resets the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading:
By writing "1" to WDRST, the watchdog timer is
reset, after which it is immediately restarted.
Writing "0" will mean no operation.
Since WDRST is for writing only, it is constantly set
to "0" during readout.

5.2.4 Programming notes

(1) The watchdog timer must reset within 3-second
cycles by software.
(2) Do not execute the SLP instruction for 2 msec
after a NMI interrupt has occurred (when f
is 32.768 kHz).
1
–
Frequency
f / 1
OSC1
f / 2
OSC1
f / 4
OSC1
f / 8
OSC1
f / 1
OSC3
f / 2
OSC3
f / 4
OSC3
f / 8
OSC3
On
Reset
Reset
Run
EPSON
Constantly "0"
0 SR R/W
–
– "0" when being read
0 R/W
0 R/W
This is just R/W
register on
E0C88862.
0 R/W
0 R/W
Off
– W
No operation Constantly "0" when
– W
No operation being read
0 R/W
Stop
OSC1
Comment
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