Epson 0C88832 Technical Manual page 61

Transmit/receive ready (SRDY) signal
When this serial interface is used in the clock
synchronous slave mode (external clock input), an
SRDY signal is output to indicate whether or not
this serial interface can transmit/receive to the
master side (external serial input/output device).
This signal is output from the SRDY terminal and
when this interface enters the transmit or receive
enable (READY) status, it becomes "0" (LOW level)
and becomes "1" (HIGH level) when there is a
BUSY status, such as during transmit/receive
operation.
TXEN
TXTRG (RD)
TXTRG (WR)
SCLK
SOUT D0 D1 D2 D3 D4 D5 D6 D7
Interrupt
(a) Transmit timing for master mode
TXEN
TXTRG (RD)
TXTRG (WR)
SCLK
SOUT
SRDY
Interrupt
(b) Transmit timing for slave mode
E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
D0 D1 D2 D3 D4 D5 D6 D7
Fig. 5.7.6.4 Timing chart (clock synchronous system transmission)
The SRDY signal changes the "1" to "0," immedi-
ately after writing "1" into the transmit control bit
TXTRG or the receive control bit RXTRG and
returns from "0" to "1", at the point where the first
synchronous clock has been input (falling edge).
When you have set in the master mode, control the
transfer by inputting the same signal from the slave
side using the input port or I/O port. At this time,
since the SRDY terminal is not set and instead P13
functions as the I/O port, you can apply this port
for said control.
Timing chart
The timing chart for the clock synchronous system
transmission is shown in Figure 5.7.6.4.
RXEN
RXTRG (RD)
RXTRG (WR)
SCLK
SIN D0 D1 D2 D3 D4 D5 D6 D7
TRXD
Interrupt
(c) Receive timing for master mode
RXEN
RXTRG (RD)
RXTRG (WR)
SCLK
SIN
TRXD
SRDY
Interrupt
(d) Receive timing for slave mode
EPSON
7F 1st data
D0 D1 D2 D3 D4 D5 D6 D7
7F 1st data 7F
55