Programmable Timer; Configuration Of Programmable Timer; Count Operation And Setting Basic Mode - Epson 0C88832 Technical Manual

5.10 Programmable Timer

5.10.1 Configuration of programmable timer

The E0C88832/88862 has two built-in 8-bit
programmable timer systems (timer 0 and timer 1).
Timer 0 and timer 1 are composed of 8-bit
presettable down counters and they can be used as
8-bit × 2 channels or 16-bit × 1 channel programma-
ble timer. They also have an event counter function
and a pulse width measurement function using the
K10 input port terminal.
Figure 5.10.1.1 shows the configuration of the
programmable timer.
Programmable setting of the transfer rate is possi-
ble, due to the fact that the programmable timer
underflow signal can be used as a synchronous
clock for the serial interface.
Furthermore, this halved underflow signal (TOUT)
can also be output externally from the R27 output
port terminal. Furthermore, the R26 output port
terminal can be used to output the TOUT signal
(TOUT inverted signal) by mask option.
OSC1
f
OSC1
oscillation
circuit
OSC3
oscillation
f
OSC3
circuit
Interrupt
Interrupt
control
request
circuit
TOUT (R27)
Output port
R27, R26
TOUT (R26)*
∗
Available when selected
by mask option
Serial
interface
E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
Input port
EVIN (K10)
K10
Timer 0 Run/Stop
PRUN0
Selector
CKSEL0
2,048 Hz
Divider
Timer 1 Run/Stop
PRUN1
Selector
CKSEL1
1/2 Selector
PTOUT CHSEL
Fig. 5.10.1.1 Configuration of programmable timer
5.10.2 Count operation and
setting basic mode
Here we will explain the basic operation and
setting of the programmable timer.
Setting of initial value and counting down
The timers 0 and 1 each have a down counter and
reload data register.
The reload data registers RLD00–RLD07 (timer 0)
and RLD10–RLD17 (timer 1) are registers that set
the initial value of the counter.
By writing "1" to the preset control bit PSET0 (timer
0) or PSET1 (timer 1), the down counter loads the
initial value set in the reload register RLD.
Therefore, down-counting is executed from the
stored initial value according to the input clock.
Programmable timer 0
Reload
PSET0
Reload
signal
RLMD0
controller
Clock
Prescaler controller
Prescaler
setting
PSC00
PSC01
Timer function setting
FCSEL
PLPOL
Pulse polarity setting
Programmable timer 1
Reload
PSET1
Reload
signal
RLMD1
controller
Clock
Prescaler
controller
Prescaler
setting
PSC10
MODE16
PSC11
8/16-bit mode
setting
EPSON
Reload data register
RLD00–RLD07
Underflow
8-bit down counter
signal
Data buffer
PTD00–PTD07
EVCNT
Event counter mode setting
Reload data register
RLD10–RLD17
Underflow
8-bit down counter
signal
Data buffer
PTD10–PTD17
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