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5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Stopwatch Timer)
5.9 Stopwatch Timer
5.9.1 Configuration of stopwatch timer
The E0C88832/88862 has a built-in 1/100 sec and
1/10 sec stopwatch timer. The stopwatch timer is
composed of a 4-bit 2 stage BCD counter (1/100 sec
units and 1/10 sec units) that makes the 256 Hz
signal that divides the f
can read the count data by software.
Figure 5.9.1.1 shows the configuration of the
stopwatch timer.
The stopwatch timer can be used as a timer differ-
ent from the clock timer and can easily realize
stopwatch and other such functions by software.
5.9.2 Count up pattern
The stopwatch timer is respectively composed of the
4-bit BCD counters SWD0–SWD3 and SWD4–SWD7.
OSC1
f
256 Hz
OSC1
oscillation
Divider
circuit
Stopwatch timer reset
SWRST
Stopwatch timer Run/Stop
SWRUN
1/10 sec counter count-up pattern
1/100 sec counter count-up pattern 1
1/100 sec counter count-up pattern 2
Count-up pattern of stopwatch timer
72
the input clock and it
OSC1
Stopwatch timer
Feedback
deviding circuit
4-bit BCD counter
1 Hz signal
Count value
Count clock
(Approximate 10 Hz signal)
Count time
Approximate 10 Hz signal
Count value
Count clock
(256 Hz)
Count time
Approximate 10 Hz signal
Count value
Count clock
(256 Hz)
Count time
Fig. 5.9.2.1
Figure 5.9.2.1 shows the count up pattern of the
stopwatch timer.
The feedback dividing circuit generates an approxi-
mate 100 Hz signal at 2/256 sec and 3/256 sec
intervals from a 256 Hz signal divided from f
The 1/100 sec counter (SWD0–SWD3) generates an
approximate 10 Hz signal at 25/256 sec and 26/256
sec intervals by counting the approximate 100 Hz
signal generated by the feedback dividing circuit in
2/256 sec and 3/256 sec intervals. The count-up is
made approximately 1/100 sec counting by the 2/
256 sec and 3/256 sec intervals.
The 1/10 sec counter (SWD4–SWD7) generates a 1
Hz signal by counting the approximate 10 Hz
signal generated by the 1/100 sec counter at 25/256
sec and 26/256 sec intervals in 4:6 ratios.
The count-up is made approximately 1/10 sec
counting by 25/256 sec and 26/256 sec intervals.
Data bus
SWD0–SWD7
1/100sec
1/10sec
4-bit BCD counter
Approximate 10 Hz
Approximate 100 Hz
26
256
0
1
2
3
26
26
25
25
(sec)
256
256
256
256
0
1
3
2
256
256
(sec)
0
1
2
3
3
3
3
(sec)
256
256
256
256
EPSON
Fig. 5.9.1.1
Configuration of
stopwatch timer
1 Hz
Interrupt
Interrupt
control
request
circuit
x 6 + 25
x 4 = 1 sec
256
4
5
6
7
8
9
26
26
25
25
26
256
256
256
256
256
2
3
4
5
6
3
2
3
2
3
256
256
256
256
256
25
sec
256
4
5
6
7
8
2
3
2
3
2
3
256
256
256
256
256
26
sec
256
E0C88832/88862 TECHNICAL MANUAL
.
OSC1
0
26
256
7
8
9
0
2
3
2
256
256
256
9
0
2
256
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