Table of Contents
Advertisement
5.8 Clock Timer
5.8.1 Configuration of clock timer
The E0C88832/88862 has built in a clock timer that
uses the OSC1 oscillation circuit as clock source.
The clock timer is composed of an 8-bit binary
counter that uses the 256 Hz signal dividing f
as its input clock and can read the data of each bit
(128–1 Hz) by software.
Normally, this clock timer is used for various
timing functions such as clocks.
The configuration of the clock timer is shown in
Figure 5.8.1.1.
OSC1
oscillation
circuit
TMRST
TMRUN
E0C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Clock Timer)
OSC1
f
256 Hz
OSC1
128
Divider
Hz
Clock timer reset
Clock timer Run/Stop
Fig. 5.8.1.1 Configuration of clock timer
5.8.2 Interrupt function
The clock timer can generate an interrupt by each of
the 32 Hz, 8 Hz, 2 Hz and 1 Hz signals.
The configuration of the clock timer interrupt
circuit is shown in Figure 5.8.2.1.
Interrupts are generated by respectively setting the
corresponding interrupt factor flags FTM32, FTM8,
FTM2 and FTM1 at the falling edge of the 32 Hz, 8
Hz, 2 Hz and 1 Hz signals to "1". Interrupt can be
prohibited by the setting the interrupt enable
registers ETM32, ETM8, ETM2 and ETM1 corre-
sponding to each interrupt factor flag.
In addition, a priority level of the clock timer
interrupt for the CPU can be optionally set at levels
0 to 3 by the interrupt priority registers PTM0 and
PTM1.
For details on the above mentioned interrupt
control register and the operation following
generation of an interrupt, see "5.14 Interrupt and
Standby Status".
The exception processing vector addresses for each
interrupt factor are respectively set as shown
below.
32 Hz interrupt:
8 Hz interrupt:
2 Hz interrupt:
1 Hz interrupt:
Figure 5.8.2.2 shows the timing chart for the clock
timer.
Data bus
Clock timer
TMD0–TMD7
64
32
16
8
Hz
Hz
Hz
Hz
Hz
Interrupt control circuit
EPSON
00001CH
00001EH
000020H
000022H
4
2
1
Hz
Hz
Interrupt
request
67
Advertisement
Table of Contents
