Interrupt Enable Register (Ier) - Hitachi HD64411 Q2 User Manual

5 . 3 . 4

Interrupt Enable Register (IER)

Bit: 15 14
TVE FRE
Initial value: 0 0
Read/Write: R/W R/W
The interrupt enable register (IER) is a 16-bit readable/writable register that enables or disables
interrupts by the corresponding flags in SR. When a bit in SR is set to 1 and the bit at the
corresponding bit position in IER is also 1, IRL is driven low and an interrupt request is sent to
the CPU.
The interrupt generation condition is as follows.
Interrupt generation condition = IRL = a+b+c+d+e+f+g
a = TVR · TVE
b = FRM · FRE
c = DMF · DME
d = CER · CEE
e = VBK · VBE
f = TRA · TRE
g = CSF · CSE
Bit 15—TV Sync Signal Error Flag Enable (TVE): Enables or disables interrupts
initiated by the TVR flag in SR.
Bit 15:
T V E Description
0 Interrupts initiated by the TVR flag in SR are disabled.
Interrupts initiated by the TVR flag in SR are enabled. When TVR·TVE = 1, an IRL
1
interrupt request is sent to the CPU.
Bit 14—Frame Flag Enable (FRE): Enables or disables interrupts initiated by the FRM
flag in SR.
Bit 14:
F R E Description
0 Interrupts initiated by the FRM flag in SR are disabled.
Interrupts initiated by the FRM flag in SR are enabled. When FRM·FRE = 1, an IRL
1
interrupt request is sent to the CPU.
13 12 11 10 9
DME CEE VBE TRE CSE
0 0 0 0 0
R/W R/W R/W R/W R/W
8 7 6 5 4
—
— — — —
— — — — —
— — — — —
3 2 1 0
— — — —
— — — —
— — — —
(Initial value)
(Initial value)
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