Display List Start Address Registers H And L (Dlsarh, Dlsarl); Multi-Valued Source Area Start Address Register (Ssar) - Hitachi HD64411 Q2 User Manual

5 . 4 . 3

Display List Start Address Registers H and L (DLSARH, DLSARL)

Bit: 15 14
DLSARH — —
Initial value: — —
Read/Write: — —
Bit: 15 14
DLSARL
* *
Initial value:
Read/Write: R/W R/W
Note: * Value is retained.
Display list start address registers H and L (DLSARH, DLSARL) are 16-bit readable/writable
registers that specify the memory area to be used as the display list.
The DLSAH field in DLSARH and the DLSAL field in DLSARL contain a total of 18 bits, and
only the upper bits (A22 to A5) of the start physical address of the display list are set in these
fields.
Bits 15 to 7 of DLSARH and bits 4 to 0 of DLSARL are reserved. Only 0 should be written to
these bits (a read will return an undefined value).
The DLSAH field in DLSARH and the DLSAL field in DLSARL retain their values in a reset.
5 . 4 . 4

Multi-Valued Source Area Start Address Register (SSAR)

Bit: 15 14
— —
Initial value: — —
Read/Write: — —
Note: * Value is retained.
The multi-valued source area start address register (SSAR) is a 16-bit readable/writable register that
specifies the memory area to be used as the multi-valued source area. Only the upper bits (A22 to
A17) of the start physical address of the source area are set in the SSAH field.
Bits 15 to 7 and 0 of SSAR are reserved. Only 0 should be written to these bits (a read will return
an undefined value).
The SSAH field in SSAR retains its value in a reset.
13 12 11 10 9
— — — — —
— — — — —
— — — — —
13 12 11 10 9
DLSAL (address A15–A5 setting)
* * *
* *
R/W R/W R/W R/W R/W
13 12 11 10 9
— — — — —
— — — — —
— — — — —
8 7 6 5 4
— — DLSAH (address A22–A16 setting)
— — * *
*
— — R/W R/W R/W
8 7 6 5 4
—
*
* * * —
R/W R/W R/W R/W —
8 7 6 5 4
— — SSAH (address A22–A17 setting)
— — * * *
— — R/W R/W R/W
3 2 1 0
* * * *
R/W R/W R/W R/W
3 2 1 0
— — — —
— — — —
— — — —
3 2 1 0
—
* * * —
R/W R/W R/W —
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