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2 . 4
Power Supply Pins
2 . 4 . 1
Normal Power Supply and PLL Power Supply
The normal power supply and PLL power supply are connected to 5 V.
CAP0 is the external capacitance pin for the multiplication circuit. Connect the specified
capacitance to this pin (figure 2-3). When multiplication is turned off, either leave the CAP0 pin
open or connect the circuit shown inside the dotted lines.
PLLV
CC
Q2
CAP0
PLLGND
Figure 2-3
2 . 4 . 2
CPU
Power Supply
Connect 5 V or 3.3 V to the CPU power supply, as appropriate. Connect 5 V for an SH703X
(SH-1), SH7064 (SH-2), or SH704X (SH-2) CPU, and 3.3 V for an SH7708 (SH3) CPU.
When a 3.3 V CPU power supply is used, the order of powering on is: normal power supply and
PLL power supply (5 V) first, followed by the CPU power supply (3.3 V). The order of powering
off is: CPU power supply (3.3 V) first, followed by the PLL power supply (5 V). (The device may
be damaged if this order is not followed.)
2 . 5
Display Interface Pins
The signals output from the display interface pins are all synchronized with the dot clock (DCLK).
2 . 5 . 1
DAC Interface
Outputs the digital pixel data synchronized with the dot clock. There is a choice of pixel data
format: 6 bits each for R, G, and B, or 8 bits each for Y, Cr, and Cb, in a 4:2:2 configuration.
Outside the display period, DO0–DO17 all go low.
22
3 kΩ
470 pF
Sample CAP0 Pin Connection Circuit
System power supply
0.1 µF
System ground
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