Unified Graphics Memory (Ugm) Display Functions; Clocks - Hitachi HD64411 Q2 User Manual

Section 3 Unified Graphics Memory (UGM) Display
3 . 1

Clocks

There are two Q2 clocks, CLK0 and CLK1. The clock used as the base for the operating clock is
input at the CLK0 pin, and the clock used as the base for the display dot clock (DCLK) is input at
the CLK1 pin.
The operating clock is the base clock for performing drawing operations, and is also used as the
base clock for UGM access. The Q2 includes an operating clock multiplication circuit that enables
a x1, x1/2, or x1/4 multiple of the operating clock to be selected for input at the CLK0 pin.
The display dot clock is the base clock for display operations, and is used to control display data
output and generate horizontal and vertical sync signals. The Q2 has a display dot clock divider that
enables a x1 or x2 multiple of the dot rate to be input at the CLK1 pin.
The relationship between the clocks and operating frequencies is summarized in table 3-1.
Table 3-1 Input Clocks and Operating Frequencies
Clock Input Pin Clock Type
CLK0 One of the clocks on the right
is the operating clock.
CLK1 One of the clocks on the right
is the display dot clock.
Functions
Operating Mode
Multiplication
on
Multiplication
off
Clock with the CLK1 frequency
Clock with 1/2 the CLK1 frequency
Clock with the CLK0
frequency, and duty adjusted
to 50%
Clock with twice the CLK0
frequency, and duty adjusted
to 50%
Clock with four times the
CLK0 frequency, and duty
adjusted to 50%
Clock with the CLK0
frequency
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