Hitachi HD64411 Q2 User Manual page 56

CLK1
EXHSYNC
DCLK (×1)
DD17 to DD0
DCLK
(×1/2 [A])
6
*
DD17 to DD0
DCLK
(×1/2 [B])
7
*
DD17 to DD0
3. The setting for the lower limit of the HDS bits is: when CLKi = 2 × DCLK, HDS ≥ 64 ×
(DCLK/CLKi); when CLKi > 2× DCLK, HDS ≥ (64+80) × (DCLK/CLKi). The unit for CLKi
and DCLK is MHz. When CLKi=2 × DCLK, use a clock with which CLKi and DCLK are
synchronized. CLKi is CLK0 when multiplication is not performed, and N × CLK0 when
multiplication is performed with a multiplication factor of N.
4. In interlace and interlace sync & video modes, the setting is: VDS8–0 ≥ 1.
5. Use a value of 4 or more for DSX.
6. When the EXHSYNC cycle is an even multiple of CLK1
7. When the EXHSYNC cycle is an odd multiple of CLK1
Table 3-3 Variables Defined by Display Screen
Variable Description
hc Horizontal scan cycle
hsw Horizontal sync pulse width
Interval between HSYNC rise and display screen horizontal
x s
display start position
xw Display screen display width per raster
v c Vertical scan cycle
vsw Vertical sync pulse width
Interval between VSYNC rise and display screen vertical
y s
display start position
yw Display screen vertical display interval
8. hsw + xs + xw < hc – 10
9. vsw + ys + yw < vc
hsw + xs
hsw + xs
hsw + xs
D0 D1 D2
D0 D1 D2
D0 D1 D2
Unit
Dot clock
Dot clock
Dot clock
Dot clock
Raster lines
Raster lines
Raster lines
Raster lines
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