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2 . 5 . 2
Video Encoder Interface
In the Q2, a video encoder interface is implemented by setting the DOT bit to 1 in the display
mode register. For example, when an NTSC encoder is used as the video encoder, 4FSC (14.31818
MHz) should be input to the CLK1 pin. As a result, the dot clock (7.15909 MHz) will be output
to the DCLK pin, the digital composite sync signal to the CSYNC pin, and FSC (subcarrier
frequency: 3.58 MHz) to the FCLK pin. In TV sync mode, CSYNC output is high.
Also, the clocks output from DCLK and FCLK are synchronized. Consequently, when the clock
output from FCLK is used as the subcarrier frequency, color drift may occur due to cross-color
effects, etc. Provisions against color drift should therefore be incorporated in the video encoder
circuit.
2 . 5 . 3
CRT Interface
Outputs the horizontal sync signal and vertical sync signal, the DISP signal indicating display
synchronization, and the ODDF signal that indicates whether the current field is even or odd for
interlace control. When synchronization is coordinated with an external device (TV or video
recorder), the horizontal sync, vertical sync, and ODDF signals are input. In a reset, the HSYNC,
VSYNC, and ODDF pins go to input mode, and therefore these pins must be fixed in a non-
significant direction (pulled up).
2 . 6
UGM Interface Pins
2 . 6 . 1
UGM Access
The Q2 allows EDO page mode DRAM to be used as the UGM. EDO page mode DRAMs can be
used with the Q2 are the Hitachi HM51 (S) 4265 Series (4-Mbit capacity, 5 V supply voltage,
256k × 16 memory configuration), the Hitachi HM5118165 Series (16-Mbit capacity, 5 V
supply voltage, 1 M × 16 memory configuration), or an equivalent product. Two of these DRAMs
can be connected to the Q2. Basically, memory with an access time of 60 ns or less should be
used.
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