Table of Contents
Advertisement
Bit 8—Dot Clock Mode (DOT): Specifies settings for the dot clock, the basic clock for the
Q2's display block.
Bit 8:
D O T
Description
0
The clock input from the CLK1 pin is used as the display dot clock.
The frequency of the clock output from the DCLK pin is the same as that of CLK1.
The frequency of the clock output from the FCLK pin is 1/2 that of CLK1.
1
A clock with 1/2 the frequency of the clock input from the CLK1 pin is used as the
display dot clock.
The frequency of the clock output from the DCLK pin is 1/2 that of CLK1.
The frequency of the clock output from the FCLK pin is 1/4 that of CLK1.
Figure 5-2 shows the display clock timing.
CLK1
Display dot clock
(internal signal)
(when DOT = 1)
DCLK
(when DOT = 1)
FCLK
(when DOT = 1)
Figure 5-2
Display Clock Timing (DOT = 1)
139
Advertisement
Table of Contents
