Hitachi Hidic EH-150 Applications Manual page 72

Preliminary Rev.03
Connection n error status (CnESR) n = 1 to 6
Bit
+1
:
+6
The error condition of each connection (1 to 6) is shown in this area.
Bit 15-7: Reserved
These bits are reserved. Usually "0" are set.
Bit 6: ASR table set-up error bit (ATE[6:1])
These bits show the error condition of Automatic Sending/Receiving (ASR) table set-up.
Bit6: ATE[6:1]
0
1
Method to clear : To clear these bits to "0", please set the correct ASR table again.
Bit 5: Send error bit (SNE[6:1])
These bits show the data sending condition of each connection.
Bit5: SNE[6:1]
0
1
Method to clear : To clear these bits to "0", please set "1" to SNC[6:1] of EC3CR.
Bit 4: Receive error bit (RCE[6:1])
These bits show the data receiving condition of each connection.
Bit5: RCE[6:1]
0
1
Method to clear: To clear these bits to "0", please set "1" to RCC[6:1] of EC3CR.
Bit 3: Receive area error bit (RAE[6:1])
These bits show the receiving data size is more than allowed size or not.
Bit3: RAE[6:1]
0
1
Method to clear: To clear these bits to "0", please set "1" to RAC[6:1] of EC2CR.
Bit 2: Discard bit (DIS[6:1])
It is shown that received data is discarded because it is received while ARE bit (Receive Ready bit) of Ready
control area is "0", when the exclusive control of the Receiving area is being carried out.
Bit2: DIS[6:1]
0
1
Method to clear: To clear these bits to "0", please set "1" DIC[6:1] of EC2CR.
Bit 1: Send timeout error bit (STE[6:1])
These bit the timeout condition during sending data.
Bit1: STE[6:1]
0
1
Method to clear: To clear these bits to "0", please set "1" to TEC[6:1] of EC1CR.
The contents of this manual might be changed without notice.
15 14 13 12 11
- - - - -
- - - - -
No error is detected in ASR table set-up.
An error is detected in ASR table set-up.
No error is detected during the data sending.
An error is detected during the data sending,
No error is detected during the data receiving.
An error is detected during the data receiving.
Size of received data dose not exceed Receive area size.
Size of received data exceeds Receive area size.
Received data has not been discarded.
Received data has been discarded.
No timeout error is detected during sending data.
A timeout error is detected during sending data.
10 9 8 7 6
- - - - ATE1 SNE1 RCE1
- - - - ATE6 SNE6 RCE6
Description
Description
Description
Description
Description
Description
8-3
Chapter 8 Register Structure
5 4 3 2 1
DIS1 STE1 OE1
RAE1
DIS6 STE6 OE6
RAE6
0