Table Of Contents - NEC mPD98409 Q&A

CHAPTER 1 PINS .................................................................................................................................... 11
Q.1.1 How does the RSTOUT_B pin operate?
CHAPTER 2 PCI INTERFACE................................................................................................................ 12
Q.2.1 How should the Cache line size of the PCI configuration register be set?
Which PCI commands are issued by the µ PD98409 when it is the master?
Q.2.2
Q.2.3 How should the Latency timer of the PCI configuration register be set?
Q.2.4 What is the function of the Retry timer in the PCI configuration register?
When the µ PD98409 is the target, what happens if an invalid command is received?
Q.2.5
Are the registers of the µ PD98409 mapped to the I/O space or the memory space?
Q.2.6
Does the µ PD98409 support the master operation of AD line driving, known as arbitration parking,
Q.2.7
if it is selected by the arbiter when there is no master to request transfer on the PCI bus?
Q.2.8 Can big endian format be used in PCI bus mode?
Q.2.9 What is the value of the Revision ID in the PCI configuration register?
Does this value change according to the version?
Q.2.10 Why is it impossible to write 0 to Status bits 31 to 27 and 24 in the PCI configuration register?
Q.2.11 What are the settings related to burst size when the µ PD98409 performs a transfer as the master?
Q.2.12 How long does it take for the EEPROM™ connection check and automatic loading?
CHAPTER 3 UTOPIA INTERFACE ........................................................................................................ 16
Q.3.1 When should the TCLAV signal be deasserted?
Q.3.2 What is the phase difference (delay) between TCLK and RCLK?
Q.3.3 The clocks of UTOPIA (TCLK and RCLK) output the BUSCLK as is. Can any other clocks be used?
Q.3.4 Can the RCLAV signal be deasserted in the middle of a cell transfer during cell-level handshaking?
Q.3.5 Does the RENBL_B signal perform the same operation in No drop mode (DR in GMR register = 1)
as in octet or cell-level handshake mode?
Q.3.6 What is the status of the Tx7 to Tx0 pins while the TENBL_B signal is inactive (high level)?
Q.3.7 An external PHY device is connected to the UTOPIA interface, but controlled by an external interface.
At this time, is it necessary to use the PHY control interface of the µ PD98409?
CHAPTER 4 CONTROL MEMORY ........................................................................................................ 18
The µ PD98409 has an on-chip control memory, but is it possible to connect additional memories
Q.4.1
such as SRAM externally?
Q.4.2 How long does it take for the control memory to be automatically initialized after reset?
Q.4.3 Are the contents of the control memory cleared to 0 when the control memory is automatically
initialized after reset?
CHAPTER 5 MAILBOX............................................................................................................................ 19
Q.5.1 Can a mailbox be set straddling over the boundary of a 64 KB area?
Q.5.2 When does the mailbox become full and how is transmission/reception stopped?
CONTENTS
...........................................................................................
.........................................................................................
..............................................................................................................
......................................................................................................................
Information S14769EJ1V0IF00
.............................................
...............................................
..............................................
.............................................................................
.............................................................................
................................................................................
........................................................
..................................................
..........................................
...........................
.............................
.....................
..............
.......
............................
.....
......
..................
....................................
........................
.................................
11
12
12
12
13
13
13
13
14
14
14
14
15
16
16
16
17
17
17
17
18
18
18
19
19
7