NEC mPD98409 Q&A page 9

Q.8.9 Pools 0 to 7 are allocated as the receive pools for Raw cells. Can all the pools from 0 to 7
be used for receiving Raw cells, or can only one of the pools from 0 to 7 be used?
Q.8.10 What is the Alert level of a receive pool descriptor? Are the settings and interrupts of the Alert level
valid for a Raw cell pool?
Q.8.11 What kind of support is there for receive VPI/VCI? When reducing from VPI/VCI 24 bits to
VPI/VCI 15 bits via a setting in the VRR register, how is the area that is invalidated by SHIFT and
MASK processed?
Q.8.12 How should the UINFO field of the receive VC table and receive indication be used?
Q.8.13 What is the Packet size field in the receive indication?
CHAPTER 9 TRANSMISSION/RECEPTION........................................................................................... 33
Q.9.1 Can the contents of the transmit/receive VC table be changed during transmission or reception?
Q.9.2 How many bits can be supported for VPI/VCI?
Q.9.3 To what part is the CRC-32 operation applied?
Q.9.4 Is the receive indication issued even when a Raw cell is received?
CHAPTER 10 COMMANDS..................................................................................................................... 35
Q.10.1 What will happen if the Tx_Ready command is issued to a VC that is transmitting a packet
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(active VC)?
Q.10.2 What will happen if the Close_Channel command is issued with an incorrect setting
for the transmit or receive VC specified by the R/T bit of the command?
Q.10.3 When accessing the control memory by using the Indirect_Access command, can two or more
addresses be accessed by issuing the command only once?
Q.10.4 How is the NOP command used?
CHAPTER 11 LOOPBACK...................................................................................................................... 37
Q.11.1 Is valid data output to the PHY side (UTOPIA interface) in loopback mode?
Q.11.2 Does the pin status of the UTOPIA interface affect the transmit/receive operations
of the µ PD98409 in loopback mode?
CHAPTER 12 REGISTERS...................................................................................................................... 38
Q.12.1 What is the function of the ADDR register?
Q.12.2 How are the ECCR and ERDR registers initialized?
Q.12.3 Can transmission/reception be temporarily halted by clearing the SE and
RE bits of the GMR register during transmission/reception?
Q.12.4 What is the value of the VER register?
CHAPTER 13 JTAG................................................................................................................................. 39
Q.13.1 How can the JTAG function be reset when JTAG is not used?
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