Can Big Endian Format Be Used In Pci Bus Mode; What Is The Value Of The Revision Id In The Pci Configuration Register? Does This Value Change According To The Version; Why Is It Impossible To Write 0 To Status Bits 31 To 27 And 24 In The Pci Configuration Register; What Are The Settings Related To Burst Size When The Μ Pd98409 Performs A Transfer As The Master - NEC mPD98409 Q&A

CHAPTER 2 PCI INTERFACE
Q.2.8

Can big endian format be used in PCI bus mode?

A.2.8
No. Only little endian format is supported by the µ PD98409.
Reference: µ PD98409 User's Manual 4.1.1 Features of PCI bus interface
Q.2.9
What is the value of the Revision ID in the PCI configuration register?
Does this value change according to the version?
A.2.9
The Revision ID is 02h, and is common to all versions. The values of the VER register, a µ PD98409 internal
register, differ depending on the version. The VER register can be used to identify the version of the device.
Reference: µ PD98409 User's Manual 4.1.2 Configuration register
Q.2.10

Why is it impossible to write 0 to Status bits 31 to 27 and 24 in the PCI configuration register?

A.2.10
Write operations to the Status register conform to the PCI standard. When 0 is written to a bit, the bit holds the
value, and when 1 is written to that bit, it is cleared to 0.
Reference: µ PD98409 User's Manual 4.1.2 Configuration register
Q.2.11
What are the settings related to burst size when the µ PD98409 performs a transfer as the master?
A.2.11
The burst size is determined by the settings of the AD, TBE, and SZ fields in the GMR register. The Cache line
size setting in the PCI configuration register is not related to the burst size. For details about the burst size, refer
to 4.1.3 PCI bus transaction in the µ PD98409 User's Manual.
Reference: µ PD98409 User's Manual 4.1.3 (6) Burst transfer
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Information S14769EJ1V0IF00