Mitsubishi Electric MELSEC-Q00U(J)CPU User Manual page 549

Ex.2)
Detecting "OPERATION ERROR" (error code: 4101) (QnU(D)(H)CPU, QnUDE(H)CPU, LCPU)
[Ladder mode]
In Example 2, in the ladder block starting from the step 15, the AND<> instruction of the step 17 or 21 is supposed
to be not executed when M0 (valid data flag) is off.
However, since the LD instruction which is always executed is used in the step 16 and 20, the AND<> instruction
of the step 17 or 21 is executed regardless of the execution status of the LD instruction in the step 15 when M1 or
M2 is on.
For this reason, even when M0 is off, if the D10Z1 value is outside the D device range, "OPERATION ERROR"
(error code: 4101) will be detected in the AND<> instruction of the step 17.
Note that the step 26 (MOV D0 D1) and the step 28 (INC D2) are not executed. For the actions to be taken to
avoid "OPERATION ERROR" (error code: 4101), refer to Page 548, Appendix 5.4.3 (2) 1) to 4).
Ex.3)
Detecting "OPERATION ERROR" (error code: 4101) (QnU(D)(H)CPU, QnUDE(H)CPU, LCPU)
In Example 3, even when M0 (valid data flag) in the step 15 is off, the AND instruction in the next step (step 16)
will be executed. For this reason, if the X10Z1 value is outside the X device range, "OPERATION ERROR" (error
code: 4101) will be detected in the AND instruction of the step 16.
For the actions to be taken to avoid "OPERATION ERROR" (error code: 4101), refer to Page 548, Appendix 5.4.3
(2) 1), 3), and 4).
Ex.4)
Not detecting "OPERATION ERROR" (error code: 4101)
[Ladder mode]
In Example 4, the AND<> instruction of the step 16 is not executed when M0 (valid data flag) of the step 15 is off.
For this reason, "OPERATION ERROR" (error code: 4101) will not be detected no matter what the D10Z1 value
is.
APPENDICES
[List mode]
[List mode]
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