HP 5334B Service Manual page 154

8-261. The oscillator is divided into three sections with each section contained on a separate printed circuit
board. The boards are connected by cable assemblies. The arrangement allows the unit to be easily disassembled
and operated in the disassembled state on the service bench. The three sections can be separated into the follow-
ing subsections:
Oscillator
Automatic Gain Control
-
Impedance Matching Amplifier
-
Voltage References
Output Buffer Amplifier
-
Oven Heater and Controller
-
Precision Voltage Reference
-
Controller Turn-On Current Limiting Circuit
-
Heater Transistor Balance Circuit
8-262. The oscillator is a Colpitts-type crystal oscillator which uses the crystal as the series inductor. The crystal
(Yl) is a "third overtone" crystal and is operated at 10 MHz. To keep the circuit from oscillating at the crystal's
fundamental, or at a different overtone, the mode suppression network consisting of C5, L2, C6, and L3 appears
capacitive only at frequencies between
9
MHz and 10.5 MHz. Below and above this frequency range, the net-
work appears inductive. This does not allow the proper phase shift around the loop and thus suppresses oscilla-
tions at all frequencies other than 10 MHz.
8-263. A n y reactance in series with the crystal causes a change in frequency. Tuning capacitor C1 is available
from the top of the oscillator outer housing. The change in reactance in C1 allows the oscillator's frequency to
be varied over a 20 Hz (2
x
lod) range.
8-264. ELECTRONIC FREQUENCY CONTROL (EFC). To allow for a fine tuning control, a varactor (CR1)
is added in parallel with the C1 tuning capacitor. The varactor's capacitance depends on the dc voltage applied
to it (reverse bias). The EFC voltage range is
+
5V to
-
5V, giving a fine tuning range of about
1
Hz (1 x lo-' ) .
Since one side of the varactor is tied to a reference (6.4V), a f u l l +5V applied to the EFC input will still keep
CR1 reversed biased. C2 and C3 keep the EFC current from flowing into the crystal circuit.
8-265. AUTOMATIC GAIN CONTROL (AGC). The Automatic Gain Control circuit consists of emitter-fol-
lower Q3 and the peak detector circuit formed by C12, C13, CR4, and CR5. The input to the AGC circuit (and
output amplifierG discussed later) is taken across capacitor C10 and applied to Q3. The signal from Q3 goes to
the peak detector which develops a dc voltage to control the crystal current. This negative control voltage forms
the lower half of a voltage-divider for the base of Q1 (with R6 and R7) which controls the bias current and gain
of Q1, thus controlling the output signal level. The voltage across C10 is proportional to the current through the
crystal. As the output of the oscillator changes, the output of the peak detector circuit changes to counteract the
oscillator signal change. The result is a stable output signal amplitude.
8-266. By adjusting the AGC voltage with R6, the amplitude for the output (at the base of Q3) can be set. R5
sets the AGC limit when R6 is at its minimum resistance.
HP
5334B
-
Service
Manual
8-34