Toshiba Strata AirLink Installation Manual page 68

RWIU System Installation
RWIU Additional Information
The WWIS has four Base Station interface connectors (J1~J4).
Figure 28 Top and Side View of the RWIU
The CPU addresses come from three octal latches that are also address buffers while the data bus
addresses are buffered by a pair of bidirectional octal transceivers connected to the various
peripheral devices.
There are eight external interrupt signals:
o INT0 – connects to the data highway receive (RX) and transmit (TX) interrupt output or to the
RX interrupt output of internal serial channel one (optional).
o INT1 – connects to the TX interrupt output of internal serial channel one.
o INT2 – connects to interrupt output of the DMA channel N0 (DMA0).
o INT3 – connects to interrupt output of the DMA channel N1 (DMA1).
o INT4 – connects to N0~3 interrupt output.
INT5 – connects to the RX interrupt output of internal serial channel one or to the data
o
highway RX and transmit TX interrupt output (optional).
o INT6 – connects to the general device interrupt output.
o INT7 – connects to the interrupt output of the optional external UART device.
The CPU has two flash (boot) memories, 128KB each, operating at 55 ns and mounted on 32-pin
sockets. The memory is expandable to two optional flash memories (512KB each, 55 ns). The total
size of program memory is 256KB or 1024KB using two memories.
The Random Access Memory (RAM) consists of two CMOS SRAM chips, 128KB (55 ns), used
as main data memories. It is expandable to 512KB (55 ns) using two additional chips. The total
size of the data memory of the CPU is 512KB.
58
S3
J13
J12
J8
RWIU (side view)
S2
J17 J16
J15 J14
RWIU (top view)
S1
J10 J9
J7
LD2
J13
JP1
JTAG
LD1
Strata AirLink Installation Guide 5/00