Mitsubishi Electric MELSEC IQ-R series Reference Manual page 447

Programmable controller
Hide thumbs Also See for MELSEC IQ-R series:
Table of Contents

Advertisement

For CPU No.4 (start input/output number: 3E30H)
ASCII code
U
3
E
3
55
33
45
33
H
H
H
H
Indirect specification of the start input/output number of the CPU module can also be performed by using the
CPU module index register.
Page 446 Access to index the network No. and start input/output number
■Device code and device number
Specify the following devices. (Page 67 Devices)
• CPU buffer memory access device (G)
• CPU buffer memory access device (HG)
For the values of device codes, refer to the following section.
Page 70 Device code list
Using the index register of CPU module, the access target device number can be specified indirectly.
Page 447 Access to index the device number
Device extension specification example
Access the buffer memory (address: 1) of the CPU No.1 (start input/output number: 03E0H) by specifying the subcommand
0082.
■Data communication in ASCII code
Extension
Subcommand
specification
0
0
8
2
0
0
U
3
30
30
38
32
30
30
55
33
H
H
H
H
H
H
H
■Data communication in binary code
Subcommand
Device number
82
00
00
00
01
00
00
00
H
H
H
H
H
H
H
H
Binary code
E3
03
H
H
Device
E
0
0
0
0
0
G
*
45
30
30
30
30
30
47
2A
H
E
H
H
H
H
H
H
Device
Extension
code
specification
AB
00
00
00
E0
03
FA
H
H
H
H
H
H
H
Device number
code
*
*
0
0
0
0
0
0
2A
2A
30
30
30
30
30
30
H
H
H
H
H
H
H
H
Appendix 1 Read/Write by Device Extension Specification
0
0
0
1
0
0
0
0
30
30
30
31
30
30
30
30
H
H
H
H
H
H
H
H
APPENDICES APPENDIX
A
H
445

Advertisement

Table of Contents
loading

This manual is also suitable for:

Melsecq seriesMelsec l series

Table of Contents