HP 81101A Reference Manual page 98

Specifications
HP 81101A Specifications
Clock / PLL Reference Input
Input Specifications
Input impedance:
Threshold:
Maximum input voltage:
Input transitions:
Input Frequency:
Minimum pulse width:
Input sensitivity:
Delay from Clock Input to TRIGGER OUT/
STROBE OUT:
Rear panel BNC connector used as:
• External system clock input: pulse frequency = input frequency.
• 5 MHz or 10 MHz frequency reference input for internal PLL.
Phase Locked Loop (PLL)
• Locks either to an external frequency reference at the PLL Ref Input
• High accuracy period (frequency) source.
• Internal triggering of bursts: the internal PLL can replace an external
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The input frequency can be measured.
Clk In (5 MHz or 10 MHz selectable) or to its internal reference.
When locked to the internal reference, period accuracy, resolution,
and jitter are improved.
When locked to an external frequency reference, the external
frequency affects these accuracies.
trigger source, while the output period is determined by the startable
oscillator.
HP 81101A
50Ω or 10kΩ selectable
–10 V to +10 V
+15 V
<100 ns
dc to max 50 MHz
10 ns
< 300 mVpp typical
12 ns typical