Mitsubishi Electric MELSEC iQ-R Series User Manual page 327

Inter-module peak current suppression function state monitor
The status of the inter-module peak current suppression function can be checked.
The status of the inter-module peak current suppression function of the channel corresponding to each bit is stored.
• 0: Stop
• 1: In execution
b15 to
0 0 0 0 0 0
Bit data from b15 to b4 are fixed to 0.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory area name
Inter-module peak current suppression function state monitor
Inter-module peak current suppression function state monitor (in the Q
compatible mode)
Inter-module peak current suppression function enable/disable monitor
Whether the inter-module peak current suppression function is enabled or disabled can be checked.
• 0: Disable
• 1: Enable
For details on the inter-module peak current suppression function, refer to the following:
Page 112 Inter-module peak current suppression function
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory area name
Inter-module peak current suppression function enable/disable monitor
Inter-module peak current suppression function enable/disable monitor (in the Q
compatible mode)
Inter-module peak current suppression function master/slave selection monitor
Whether the inter-module peak current suppression function has been set to Master or Slave can be checked.
• 0: Slave
• 1: Master
For details on the inter-module peak current suppression function, refer to the following:
Page 112 Inter-module peak current suppression function
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory area name
Inter-module peak current suppression function master/slave selection monitor
Inter-module peak current suppression function master/slave selection monitor
(in the Q compatible mode)
b4 b3
0 0 0 0 0 0 CH4 CH3
b2 b1 b0
CH2 CH1
CH1 CH2
2100
1280
CH1 CH2
2101
1281
CH1 CH2
2102
1282
CH3 CH4
CH3 CH4
CH3 CH4
APPX
Appendix 3 Buffer Memory Areas
A
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