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Functional Description
4
PhoenixBIOS Description
Soft Reset
4-8
this document. The BIOS specification defines a way of reading this
information through the BIOS using Plug and Play BIOS functions 50h -
5fh.
The specification defines various structures used to store system
information as data bytes and/or as ASCII strings. For example, the Type
0 structure stores BIOS information and the Type 1 structure stores system
information. The Type 11 structure provides additional information about
the system using reserved, custom/OEM strings defined by the
manufacturer.
The CPN5365 uses the PhoenixBIOS to provide initial hardware
configuration for local devices and local operating system boot.
The CPN5365 BIOS is similar to the CPIP5365 BIOS. Refer to
C, Related
Documentation, for a listing of related documentation that
describes the PhoenixBIOS, PCI-to PCI bridge configuration, and
programming information. Refer to
Bank on page 4-7
for additional information about the CPN5365 BIOS.
You can generate a soft reset from your keyboard, the watchdog timer, or
the front panel push button in Soft Reset Mode. The BIOS preserves as
much of the system memory state as possible.
A CPN5365 circuit monitors system power and provides the PWROK
signal to the PIIX4E. The PIIX4E distributes the reset to the rest of the
board by generating the CPU, PCI, and IDE resets. You can also reset the
board using the front panel reset switch and the FPGA watchdog timer.
You can program the Watchdog Timer and the front panel push button
switch to generate a soft reset. Refer to
Registers on page 4-6
Jump to User Code in Alternate Flash
Field Programmable Gate Array
for programming information.
Computer Group Literature Center Web Site
Appendix
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