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User UART serial
line reset jumpers:
I
C interface
2
jumpers:
Audio amplifier
jumpers:
Note: If the reset condition set by these jumpers is met, the D10 LED diode
will shine and the CPU will be reset.
J1
User UART Serial line reset - polarity selection
:
In the 1-2 position, the "1" level on the DTR
In the 2-3 position, the "0" level on the DTR
If the reset condition set by this jumper is met, the D11 LED diode will shine
and the CPU will be reset.
Note: The User UART DTR
logic only if there is a jumper in the 7-8 position on the J23 header.
J14, J15
The
jumpers select one of the two available I
or FPGA's one. This way, the selected interface is connected to serial EEPROM
2
and I
C connector as well.
J14: SCL source selection
In the 1-2 position, the FPGA I
SCL signal.
In 2-3 position, the CPU's I
J15: SDA source selection
In the 1-2 position, the FPGA I
signal.
In 2-3 position, the CPU's I
J13: WP setting
If short, this jumper pulls down the WP (write protect) pin of the serial
EEPROM.
Note: For the description of the Write protect feature, see the EEPROM
datasheet.
J38: Audio signal source selection
In the 1-2 position, the PPG0 pin of the CPU is selected as input for the
audioamplifier.
In the 2-3 position, the SGO pin of the CPU is selected.
Note: the MB90F543 CPU does not have the SGO (sound generator
output) pin.
line will cause the CPU reset.
F
line will cause the CPU reset.
F
line is connected to the User UART reset
F
2
C interface is selected as the source for the
2
C interface is selected.
2
C interface is selected as the source for the SDA
2
C interface is selected.
58
58
58
58
2
C interfaces –CPU's I
2
C
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