The Mainboard Programmer's Reference; Register Addresses And Chip Selects; Interrupts - Fujitsu DevKit16 User Manual

The Mainboard
Programmer's Reference
This section describes internal registers of the FPGA chip, which provides the
biggest portion of the Mainboard functionality. The FPGA is connected to the
CPU external bus, so it is necessary to program all the CPU external bus pins
(including the CLK and /WRL pins) to the external bus mode with the 8-bit
access to the 0C0H-0FFH area. In Processor Expert environment, this is done
automatically when using any of the "MB90540 external bus" project templates.
R E G I S T E R A D D R E S S E S
FPGA I/O space is mapped to CPU bank 0 and starts from 0C0H
System Control Registers:
2
I C:
UART:
Add-on FPGA output only port:
Simulated CPU ports:
Add-on FPGA ports:
Keyboard Controller:
FPGA EEPROM :
WWLED:
*
CSUSERIO :
*The CSUSERIO signal is generated by the FPGA when accessing this area. It is provided on the
Prototype connector.
I N T E R R U P T S
The interrupts in the following table are used by the Mainboard and should not
be used by an user harware:
INT0 Hardware breakpoint, User Key Button
INT1 User (FPGA) UART
INT2 Keyboard
2
INT3 FPGA I C
A N D C H I P
0C0H – 0C8H
0C9H – 0CFH
0D0H – 0D3H
0D7H
0D8H – 0DFH
0E0H – 0E7H
0EAH, 0EBH
0EFH
0E8H, 0E9H
0F0H – 0FFH
61 61
61 61
9 9
Chapter Chapter
S E L E C T S