Add-On Fpga Ports - Fujitsu DevKit16 User Manual

DDR3 15
Addr.: DF D37
H
When reading the register, last value written to it is returned.
Pins are controlled as described below:
0 = Input mode
1 = Output mode
Note: Pull-up resistors 47K are internally connected to port pins.
A D D - O N F P G A
These ports are provided with FPGA content version 1 and can be found on
FPGA User Programmable Pins connector.
Registers
Base Address: 0000E0
(1) Port data registers
PDR4 7
Address:E0 P07
H
PDR5 15
Address: E1 P17
H
PDR6 7
Address: E2 P27
H
PDR7 15
Address: E3 P37
H
14 13 12 11
D36 D35 D34 D33
P O R T S
H
6 5 4 3
P06 P05 P04 P03
14 13 12 11
P16 P15 P14 P13
6 5 4 3
P26 P25 P24 P23
14 13 12 11
P36 P35 P34 P33
63 63
63 63
10 9 8 Initial
value
D32 D31 D30 00
2 1 0 Initial
value
P02 P01 P00 00
10 9 8 Initial
value
P12 P11 P10 00
2 1 0 Initial
value
P22 P21 P20 00
10 9 8 Initial
value
P32 P31 P30 00
Acces
s
R/W
H
Access
R/W
H
Access
R/W
H
Access
R/W
H
Access
R/W
H