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S Y S T E M
C O N T R O L
The system control registers allows to check and control Devkit16 configuration.
(1) System control DIP switches status
SCDS[7:0]
7
Address: C0
USW
H
Read/Write
(R)
Initial Value
(X)
This register allows to read the current state of mainboard System control DIP
switches (SW1).
Writing to this register has no meaning.
(2) System Configuration Register
SCR[7:0]
7
Address: C1
RESET MirrorFF
H
Read/Write
R/W
Initial Value
(0)
The value in this register controls the system configuration.
MD0-MD2:
ADR/IO:
FLASH 8/16:
Note: setting of this bit should correspond with the CPU external data bus
width configuration of the memory space where the mainboard's FLASH
memory is mapped - see the "Bus control signal selection register"
description on page 277 in the "F
Microcontroller MB90540/545 series hardware manual".
SWAP FLASH/RAM: if 1 then Main board RAM is mapped to upper
MirrorFF:
R E G I S T E R S
6
5
4
FLASH8/16
UART0/1
SWAP
(R)
(R)
(R)
(X)
(X)
(X)
6
5
FLASH8/16
SWAP
R/W
R/W
R/W
(1)
(X)
(X)
these bits directly control the state of CPU pins MD0-
MD2. The initial value of this register is affected by
the state of the mainboard System control DIP
switches (SW1) – when the power is applied to the
mainboard or mainboard Reset button is pressed, the
state of UMD0-2, FLASH8/16, SMALL and SWAP
switches is copied to it.
When '1', the A16-A23 CPU pins can be switched to
general I/O mode. For description of this feature, see
the "Mainboard User Reference" chapter. When '0',
the A16-A23 pins are expected to behave as address
signals.
if 1 then 16bit access is selected for main board
FLASH
2
MC-16LX Family, 16-Bit
memory block - UMB, Main board FLASH is in LMB
else RAM is LMB and FLASH is UMB.
if 1 then any access to address range 4000H - 0FFFFH
is mapped to the FF4000H-FFFFFFH range. The
73
73
73
73
3
2
Adr/Io
UMD2
(R)
(R)
(X)
(X)
4
3
2
Adr/Io
MD2
R/W
R/W
(X)
(X)
1
0
UMD1
UMD0
(R)
(R)
(X)
(X)
1
0
MD1
MD0
R/W
R/W
(X)
(X)
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