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[Bit 5] BI:
Break Indicate bit is set when a Break Signal was received. It
can be cleared by reading the LSR
[Bit 4] FE:
Framing error bit is set when stop bit is 0 during normal
character (not a Break Signal) reception. Can be cleared by
reading the LSR
[Bit 3] OE:
Overrun error bit is set when a new character is received but the
previous has not been read from the SDAT register yet.
[Bit 2] DR:
Data Ready bit is set when there is a new character in the receive
buffer.
(4) Baud register
BDR
7
Address: D3
---
H
Read/Write
(---)
Initial Value
(---)
The BD3-BD0 bits form the Baud Rate divisor BD. The resulting baud rate can
be computed as
Baudrate=115200/BD. In the next table you can find the most typical values of
BD:
BD
0
disable baud generator
1
115 200
2
57600
3
38400
6
19200
12
I
C
2
2
The I
C interface is provided for acceleration of operations with the I
EEPROM memory that is mounted on the Mainboard. Therefore, the
interface was simplified to save the FPGA resources, that can be used for
user design. The interface implementation is based on the Philips I
specification ver. 2.0 with these limitations:
Slave mode is not supported
Multi-master mode of operation is not supported
6
5
4
---
---
---
(---)
(---)
(---)
(---)
(---)
(---)
Rate
9600
67
67
67
67
3
2
1
BD3
BD2
BD1
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
0
BD0
(R/W)
(0)
2
C
2
C
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