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Barracuda PDA Maintenance
GPIO 9:2
when dual-panel color or 16 bit TFT operation is programmed, GPIO pins are used as the additional,
required LCD data lines to output pixel data to the screen.
L_PCLK
Pixel clock used by the LCD display to clock the pixel data into the line shift register. In passive mode.
pixel clock transitions only when valid data is available on the data pins. In active mode, pixel clock
transitions continuously and the ac bias pin is used as an output to signal when data is available on
the LCD's data pins.
L_LCLK
Line clock used by the LCD display to signal the end of a line of pixels that transfers the line data from
the shift register to the screen and increment the line pointers. Also, it is used by TFT displays as the
horizontal synchronization signal.
L_FCLK
Frame clock used by the LCD displays to signal the start of a new frame of pixels that resets the line
pointers to the top of the screen. Also, it is used by TFT displays as the vertical synchronization sibnal.
L_BIAS
AC bias used to signal the LCD display to switch the polarity of the power supplies to the row and
column axis of the screen to counteract DC offset. In TFT mode, it is used as as the output enable
to signal when data should be latched from the data pins using the pixel clock.
The pixel clock frequency is derived from the output of the on-chip PLL that is used to clock the CPU ( CCLK )
and is programmable from CCLK/6 to CCLK/514. each time new data is supplied to the LCD data pins, the
pixel clock is toggled to latch the data into the LCD display's serial shifter.
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