NEC Barracuda Service Manual page 75

4. Pin Descriptions of Major Components
4.1 Intel® StrongARM* SA-1110 Microprocessor-3
Name Type
ROM_SEL IC ROM select. This pin is used to configure the ROM width. It is either
grounded or pulled high. If ROM_SEL is grounded, the ROM width
is 16 bits. If ROM_SEL is pulled up, the ROM width is 32 bits.
PXTAL IC Input connection for 3.686-MHz crystal (non-CMOS threshold).
PEXTAL OCZ Output connection for 3.686-MHz crystal (non-CMOS level).
TXTAL IC Input connection for 32.768-kHz crystal (non-CMOS threshold).
OCZ Output connection for 32.768-kHz crystal (non-CMOS level).
TEXTAL
OCZ Power enable. Active high. PWR_EN enables the external VDD
PWR_EN
power supply.
Deasserting it signals the power supply that the system is going into
sleep mode and that the VDD power supply should be removed.
BATT_FAULT IC Battery fault. Signals the SA-1110 that the main power source is
going away (battery is low or has been removed from the system).
The assertion of BATT_FAULT causes the SA-1110 to enter sleep
mode. The SA-1110 will not recognize a wake-up event while this
signal is asserted.
VDD_FAULT IC VDD fault. Signals the SA-1110 that the main power supply is going
out of regulation (shorted card is inserted). VDD_FAULT will cause
the SA-1110 to enter sleep mode. VDD_FAULT is ignored after a
wake-up event until the power supply timer completes (approximately
10 ms).
nRESET IC Hard reset. This active low signal is a level-sensitive input used to
start the processor from a known address. A low level will cause the
current instruction to terminate abnormally, and the on-chip caches,
MMU, and write buffer to be disabled.
When nRESET is driven high, the processor will restart from address
0. nRESET must remain low until the power supply is stable and the
internal 3.686-MHz oscillator has come up to speed. While nRESET
is low, the processor will perform idle cycles.
nRESET_OUT OCZ Reset out. This signal is asserted when nRESET is asserted and
deasserts when the processor has completed resetting. nRESET_OUT
is also asserted for "soft" reset events (sleep and watchdog).
nTRST IC Test interface reset. Note this pin has an internal pull-down resistor
and must be driven high to enable the JTAG circuitry. If left
unconnected, this pin is pulled low and disables JTAG operation.
TDI IC JTAG test interface data input. Note this pin has an internal pull-up
resistor.
OCZ JTAG test interface data output. Note this pin does not have an
TDO
internal pull-up resistor.
IC JTAG test interface mode select. Note this pin has an internal pull-up
TMS
resistor.
Barracuda PDA Maintenance
Description Name Type
TCK IC JTAG test interface reference clock. This times all the transfers on the
JTAG test interface. Note this pin has an internal pull-down resistor.
TCK_BYP IC Test clock PLL bypass. When TCK_BYP is high, the TESTCLK is
used as the core clock in place of the PLL clock; when low, the
internal PLL output is used. This signal has no relation to the JTAG
TCK pin.
TESTCLK IC Test clock. TESTCLK is used to provide the core clock when
TCK_BYP is high. It should be tied low if TCK_BYP is low. This pin
should be used for test purposes only. An end user should ground this
pin.
VDD — Positive supply for the core. Nine pins are allocated to this supply;
eight pins are labeled VDD. The ninth pin, labeled VDDP is
dedicated to the PLL supply and should have its own dedicated
decoupling capacitor. Also, it should be tied directly to the VDD
power plane with the other eight VDD pins.
— Positive supply for the pins. See Chapter 14 for a count of VDDX
VDDX
pins. All of the pins allocated to VDDX (labeled VDDX1, VDDX2,
and VDDX3) should be tied directly to the VDDX power plane.
VDDX3 should have its own dedicated decoupling capacitor.
VSS — Ground supply. Nine pins are allocated to VSS, including one for the
PLL.
VSSX — Ground supply for the I/O pins.
Description
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