Hitachi EC701HP Operation Manual page 19

Section 1 - Introduction (UHF Digital TV Transmitters)
E-Compact - Air Cooling - ATSC - High Power
Description of main circuits:
Equalizer input circuit ASI 1 e 2
Equalize and convert DVB-ASI signal into a differential LVDS signal to the FPGA.
Circuit Cable Driver of the outputs ASI 1 e 2
Converts the LVDS signal provided by the FPGA to DVB-ASI electrical standard. The two ASI
outputs have the same content.
GPS Ublox (Optional)
GPS receiver module with input for active antenna (amplified) supplied with +5 V (via coaxial
cable) and output PPS (Pulse Per Second) with LVTTL levels.
PPS Input and Output
Uses components schmitt trigger as interface, has high input impedance (> 1M) and low
output impedance (~ 35). Compatible with TTL/ LVTTL level input and LVTTL output.
10MHz Input and output
The input circuit is a zero crossing detector with an impedance of 50 and AC coupling. Provides
a signal of 10MHz square with LVTTL levels for the FPGA for input between 0 and +10 dBm.
The output with an impedance of 50 provides a sinusoidal signal with +8 dBm ~ 700mV DC
level to a load 50or 4Vpp and 1.5 V average for high impedance loads (> 1M). The output
signal is a sample of 10MHz from the OCXO, a temperature-controlled oscillator and a frequency
range of approximately + / -1.5 ppm or + / - 15Hz.
SYSCLK – System's Clock
The sysclk circuit is basically composed of two main components, the first is the clock generator
(CI HMC830LP6) that receives the reference of 10MHz and generates a signal of 1377.56643358
MHz (8xSYS_CLK) through the fractional PLL and integrated VCO.
The second component is the clock distributor (IC AD9510) which performs a frequency division
of 8 and 16 for generating the signs of 172.195804197 MHz (FPGA_CLK, and DAC_CLK and
test point SYSCLK) and 86.09790209 MHz (ADC_CLK) respectively.
This circuit is configured via SPI interface, by the microcontroller A512 during system startup.
The Lock Detect output is used for verification of this circuit.
The frequency of the system clock for 6MHz BW is achieved through tithe 8192 * 10
Digital Modulator
The ASI reception blocks, remultiplexing, modulation and corrections are described through the
languages VHDL and Verilog and synthesized using the Quartus II software. A SOC (System on
a Chip) using Nios processor is also present for the execution of the functions of conFiguretion,
control and communication of the system using functions described in ANSI C language.
The FPGA basically makes the treatment of the input transport stream and modulates this
information according to the ATSC standard, generating a complex digital FI (I and Q signals of
16-bit signed complementing 2) with a sampling rate of 86.0979 MSPS. Also performs the linear
and non-linear pre-correction, the capture and storage of internal signals and of feedback to
implement the tasks of pre-correction and measures.
Manual Rev. 0.1 - February 2018
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