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HP 811 OA Se
r
vice G
u
i
d
e
Device
BU
S Interface
Thi s sect i on i s on sch emat i c 3 Α.
7- 1 6
F
unctio
n
al Desc
r
ip tio
n
Th e DBI ( Device Bu s Interface) is imple me nted with an
I
S IS
( In tegrated Seri al Inter nal
S
upp ort)
I
C on each board.
D
ecoder
U
26
p rovides enable si g n als
f
or each
o
f
t
hese, up to α
m
aximum
o
f 5 .
The MPU communicates ser ially wit h the DBI t hrough its internal
Qu eued Seri al M odule (QS M ).
Interrupts
Thi s sectio n i s on schemat i c 3Α .
Th e Gen eral Purp ose Timer (G PT) handles the
f
ollowin g external
interrup ts :
ι K eyb oard
ι
R
otar y Pul se Generator (RP G)
ι HP- ΙΒ
ι Devi ce Bu s Interface (DBI) .
Wh en
a
ny
o
f t h ese de vices
h
ave data, they signa l t his to the MPU on
t h ese inputs. Two a ddi tion al interrupts are used by th e MPU :
ι B eep er Sto p
ι P SOS tick - P SOS
i
s an op erating system used by the
Mi crop rocessor . The 'tick '
p
rovides α real-time interr upt
f
or su ch
tasks as schedu ling .
Display
E na
b
li
n
g
T
hi s sect io n is on sch emati c 3Α.
Thi s descr ip tio n does not cover the Display U nit, whi ch can be
con s i dere d as α repl aceable unit .
The Dis play is b lank ed at system ini ti alisat io n to
p
re vent the display
o
f ran dom information.
I
t i s activated by w rit in g to
U
24 to set s ign al
LDIS BL .
S hift register
U
23 controlli ng
U
33
p
rovi des correct setup and hol d
times
b
etwee n Read/Write a nd V alid
D
ata Bu s. Addi tionally, t he
so ftw are wai ts 2μ s
b
et ween eac h R ead/Write cy cle.
R
es i stors
R
20 -
R
22 redu ce o v ers h oot .
B
uffe
r
i
n
g
Thi s secti o n i s on sc h ematic 3 D.
Th e
m
ain reason for buffering is to disable the data bus if t his b us
i
s
used
f
or access ot h er t han to t he display uni t . Thi s is
b
ecause only
lines insi de th e s hi el ded case should toggle - thus minimising RFL
Control s ig n al s are al so buffered . Buffering
i
s
p
rovided by U 20 to
restore data ri se an d
f
al l tim es due to t he act io n
o
f RFI fil tering.
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