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HP 81103Α 10 V/2 ns Output Ch annel
2-1 0
Specification s
O
utputs
Tra nsition Times
Measured between 10% and 90% of
a
mplitude. Can be entered as
l
eading/trailing edge or % ο
o
f width .
Δ
Range :
2 .00 ns το 200 ms
M
i n . transit i o n : Ι < 2 .0 ns
f
or levels wi thin ξ5 V wi n dow
ς 2 .5 ns for all
l
evels
A
cc u racy :
1 ξ 10% ο ±200 ρ s
1 .4 ns typica l for E C L l e vels (20% to 80% of
a
mp litude)
L
inearity :
13% ty pical for transitions >100 ns
Leading and trailing edges can be
p
rogrammed independently within
t
he
f
ollowing ranges (Maximum ratio 1 :20) :
10
n
s
100
ns
1 us
10
u
s
100 υ5
2
n
s Ι
20
n
s
200
n
s
2 us
20 ;
u
s
F
igu re 2-1 .
L
eading/Traili ng Edge ranges
Source impedance :
se l ectable 50Ω or 1 kΩ ξ 1% ty p ical
(48 Ω or 500 Ω wit h Ad d ed C h anne l s)
Maximum exter nal voltage : ξ 25 V
S
hort circuit current :
ξ 400 mA max .
Normal/complement :
ON/OFF
:
Limits :
D
ynamic Crosstal k
External
L
oad compensation
selectable
relays connect/disconnect out p ut (H i Z) .
hi g h and low
l
evels can b e
l
i mi ted to p rotect t h e DUT .
ς 0 .1% ty pica l
F
or
l
oads 54 50 Ω, the actual load impedance can
b
e entered to correct
the output values into α static
l
oad .
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