HP 8110A Service Manual page 226

150 mhz pulse generator
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Me
m
ory Ca
rd
Con
n
ector
B
oa
rd
Th e M em or y Car d is also buffered
f
or si mil ar reaso ns, as we ll as to
p
reven t dam age to the in strument in t he event of acci dental mi s use
of t h e Mem ory Card Conn ector.
RP
G
T
hi s sect i on is on sch emati c 3 D.
T
hi s descript io n does n ot cover t he RPG, whi c h can
b
e cons i dered as
α replaceabl e uni t .
U
43C buffers the RP G interr upt signal.
U
43D provi des t he MPU
wi t h α bu ffered
d
irect ion al signal.
B
eeper
T
hi s secti o n i s on schem at ic 3Α.
D
rive
f
or the
b
eep er comes direct ly from th e MPU
a
nd
f
rom invertor
U40 A . Wh e n th e MPU
g
iv es α hig h
o
utput
l
e v e l,
U
40A takes the
oth er s i de of t h e
b
eep er
l
ow . Th e reverse appli es wh e n the MPU
g
ives α
l
ow
o
utput
l
e vel, revers ing the
b
ee per across t he po wer supply
at t h e
f
re quen cy th at th e MPU pin toggles . Th e firmware
p
rovi des α
numb er of frequ encies
f
or the
b
ee p er.
HP- ΙΒ Interface
Thi s section i s on sc hematic 3Β .
HP 8110 Α Service G
u
ide
U 28 d ivides t h e system
c
lock frequency
b
y 4 to p roduce t he HP-1B
cl ock at app roximately 4.2 MHz .
U
10
i
s the HP-1B con troller. The
LDRD (Lo w D ata
R
ead) si g nal is inv erted by U40B to become
HDRD (High D ata
R
ead) . The
D
atabus i s buffered by U 21 .
D
ata
an d co n tro l lines are buffered by U11 and
U
12.
Keyboard
Thi s secti on i s on schemati c 3C .
Wh en e v er α
k
ey is
p
ressed an interr upt sign al is gener ated by gate
U
38 .
U
25 sequ en ti ally latches data to
p
rod uce 4 columns wit h α 'travellin g'
l
o w le v el. If α key is
p
ressed it conn ects α column to one of 8 r o w s
for m ed b y th e inpu ts to
l
atch U 22. By reading th e 12 bi t 'w ord' t hus
f
or m ed, th e MPU can calculate whi ch key was
p
ressed, as each k ey
h as α uniqu e row -column combin ati on
Thi s sect io n is on sch emat ic 3 D .
Thi s descrip ti on does not co ver t he M emor y Card, whi ch can
b
e
co n s i dered as α replaceable uni t .
Buffering of Address and
D
ata buses
i
s provi ded by U 15 - U19
F
unctio
n
al Description 7-17

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