Mode-Specific Guidelines - Dell 0G8DW Installation And Service Manual

Configuration
Configuration 9
Configuration 10
Configuration 11
Configuration 12
Configuration 13
Configuration 14

Mode-specific guidelines

The configurations allowed depend on the memory mode selected in the System BIOS.
Table 44. Memory operating modes
Memory Operating Mode
Optimizer Mode
Mirror Mode
Single Rank Spare Mode
Description
20x 32 GB RDIMMs, 4x
NVDIMM-Ns
12x 16 GB RDIMMs, 6x
NVDIMM-Ns
12x 32 GB RDIMMs, 6x
NVDIMM-Ns
18x 32 GB RDIMMs, 6x
NVDIMM-Ns
12x 16 GB RDIMMs, 12x
NVDIMM-Ns
12x 32 GB RDIMMs, 12x
NVDIMM-Ns
Memory population rules
RDIMMs
Processor1 {A1, 2, 3, 4, 5, 6, 7, 8,
9, 10}
Processor2 {B1, 2, 3, 4, 5, 6, 7, 8,
9, 10}
Same for all 12x RDIMM
configurations. See
Configuration 1.
Same for all 12x RDIMM
configurations. See
Configuration 1.
Processor1 {1, 2, 3, 4, 5, 6, 7, 8,
9}
Processor2 {1, 2, 3, 4, 5, 6, 7, 8,
9}
Same for all 12x RDIMM
configurations. See
Configuration 1.
Same for all 12x RDIMM
configurations. See
Configuration 1.
Description
The Optimizer Mode if enabled, the DRAM controllers operate
independently in the 64-bit mode and provide optimized memory
performance.
The Mirror Mode if enabled, the system maintains two identical
copies of data in memory, and the total available system memory is
one half of the total installed physical memory. Half of the installed
memory is used to mirror the active memory modules. This feature
provides maximum reliability and enables the system to continue
running even during a catastrophic memory failure by switching
over to the mirrored copy. The installation guidelines to enable
Mirror Mode require that the memory modules be identical in size,
speed, and technology, and they must be populated in sets of 6 per
processor.
Single Rank Spare Mode allocates one rank per channel as a spare.
If excessive correctable errors occur in a rank or channel, while the
operating system is running, they are moved to the spare area to
Installing and removing system components
NVDIMM-N
Processor1 {A11, 12}
Processor2 {B11, 12}
Processor1 {A7, 8, 9}
Processor2 {B7, 8, 9}
Processor1 {A7, 8, 9}
Processor2 {B7, 8, 9}
Processor1 {A10, 11, 12}
Processor2 {B10, 11, 12}
Processor1 {A7, 8, 9, 10, 11, 12}
Processor2 {B7, 8, 9, 10, 11, 12}
Processor1 {A7, 8, 9, 10, 11, 12}
Processor2 {B7, 8, 9, 10, 11, 12}
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