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Register Offset
Register Descriptions
WRITE Registers
READ Registers
base + 00
15
14
16
Write
Read
Device
Class
84 HP E1351A/53A Register-Based Programming
The register offset is the register's location in the block of 64 address bytes.
For example, with a LADDR of 112 the multiplexer's Scan Channel Delay
Register has an offset of 08
the offset is added to the base address to form the register address:
DC0016 + 0816 = DC08
1FDC00
or
56,320 + 8 = 56,328
2,087,936 + 8 = 2,087,944
There are six WRITE and two READ-only registers on the multiplexer.
You can READ-back three of the WRITE registers. This section contains a
description and a bit map of each register. Note that the bit names with an *
after them are True (asserted) when low (zero). An X represents a "do not
care" situation and a 1 always represents 1.
The following WRITE registers are located on the multiplexer:
•
Status/Control Register (base + 04
•
Scan Control Register (base + 06
•
Scan Channel Delay Register (base + 08
•
Scan Channel Configuration Register (base + 0A
•
Direct Channel Configuration Register (base + 0C
•
Direct Control Register (base + 0E
There are two READ-only registers and three READ-back registers.
•
Manufacturer ID Register (base + 00
•
Device Type Register (base + 02
•
Status/Control Register (base + 04
•
Scan Control Register (base + 06
•
Scan Channel Delay Register (base + 08
Manufacturer ID Register
13
12
11
10
Address
Space
. When you write a command to this register,
16
16
+ 08
= 1FDC08
16
16
16
16
16
16
9
8
7
6
Undefined
Manufacturer ID
(A16 outside the command module)
(A16 inside the command module)
(A16 outside the command module)
(A16 inside the command module)
)
16
)
)
16
)
16
)
16
)
16
) READ-only
16
) READ-only
)
16
)
)
16
5
4
3
2
Appendix B
1
0
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