Table of Contents
Advertisement
Status/Control
Register
base + 04
15
14
16
Write
Read
Card Reset (CRD RST)
Interrupt Request
Enable (IRQ EN)
Direct (DIR)
Trigger Internal
(TRG INT)
Interrupt Request
Enable (IRQ EN*)
Interrupt Request (IRQ*)
Busy (BSY*)
Appendix B
The Status/Control WRITE register is used to reset the module, enable
interrupts, choose direct or scan list control of the channels and to internally
trigger channel closing. The READ register indicates if interrupts are
enabled, if there is an interrupt and if the module is busy.
13
12
11
10
Undefined
Undefined
Writing a one (1) to bit 0 resets the multiplexer. Writing a zero turns the
reset function off. You must write a zero after a reset or the module will not
operate. The Reset conditions are: all Enables are set false, clear scan list,
scan mode enabled (direct bit set 0), DELAY is l
opened.
Writing a one (1) enables the card to generate interrupts, a zero (0) disables
it. Enabling this bit puts a zero (0) in IRQ EN*.
Selects between direct control and scan list control. A zero (0) indicates
scan list control and a one (1) indicates direct control. For scan list control
the Direct Registers (base + 0C, base + 0E) are invalidated. For direct
control the Scan Channel Configuration Register is invalidated.
Writing a one (1) immediately advances a channel on the scan list, a zero
(0) is the idle state. Bit is automatically set back to zero (0) upon channel
advance.
Reading a zero (0) indicates enabled, reading a one (1) indicates disabled.
Reading a zero (0) indicates an interrupt, a one (1) indicates no interrupt.
This bit remains one (1) if IRQ EN is disabled. Interrupt remains set until
Card Reset or interrupt has been acknowledged.
This bit is set zero (0) during channel closing and the delay period. Triggers
will not be accepted. BSY* is unasserted at the beginning of the Channel
Closed pulse. If a trigger occurs during the Channel Closed pulse, the pulse
is terminated and the channel is advanced. Operates only with downloaded
scan list (DIR is zero).
HP E1351A/53A Register-Based Programming 87
9
8
7
6
X
X
1
1
5
4
3
2
X
TRIG
DIR
IRQ
INT
EN
1
BSY*
1
1
IRQ* IRQ
µ
sec and all channels
1
0
X
CRD
RST
EN*
Advertisement
Table of Contents
