Pioneer PRA-BD11 Service Manual page 88

Sdi aes/ebu input board, sdi aes/ebu output board
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1
No.
Pin Name
31
TP08
A
32
GND
33
TP09
34
TP10
35
TP11
36
TP12
37
TP13
38
Vccint
39
Vcco
GND
40
41
TP14
42
TP15
B
43
TP16
44
DINB_EXIST
45
SDI_VALID
46
SDI_NP
47
AES_LRCK
48
AES_DAI
49
AES_BCK
50
M1
51
GND
52
M0
C
Vcco
53
M2
54
N.C.
55
N.C.
56
57
20_V
58
20_H
59
20_STD0
60
20_STD1
61
20_STD2
62
20_RESET#
D
63
14_CE
64
GND
65
Vcco
66
Vccint
67
14_CD
68
14_CC
69
14_CB
70
14_CA
71
14_C0
72
GND
73
14_C
E
74
14_CS12
75
14_SEL
76
Vccint
77
CLK_128FS
78
Vcco
GND
79
CLK_27MFPGA
80
F
88
1
2
I/O
O
FPGA test signal output (Not connected at AVIB side)
Digital GND
O
FPGA test signal output (Not connected at AVIB side)
O
FPGA test signal output (Not connected at AVIB side)
O
FPGA test signal output (Not connected at AVIB side)
O
FPGA test signal output (Not connected at AVIB side)
O
FPGA test signal output (Not connected at AVIB side)
Core power supply (2.5V)
I/O power supply (3.3V)
Digital GND
O
FPGA test signal output (Not connected at AVIB side)
O
FPGA test signal output (Not connected at AVIB side)
O
FPGA test signal output (Not connected at AVIB side)
O
A signal to judge that DINB is mounted H: DINB is mounted, L: DINB is not mounted
The signal which shows whether a SDI signal is valid
O
H: A valid SDI signal is input, L: There is not input signal, or a invalid SDI signal is input
O
The signal which shows whether a SDI signal is NTSC or PAL H:NTSC, L:PAL
O
LR clock output for AES/EBU
O
Data output for AES/EBU
O
Audio clock output for AES/EBU
I
Configuration setting (default "L", master serial mode)
Digital GND
I
Configuration setting (default "L", master serial mode)
I/O power supply (3.3V)
I
Configuration setting (default "L", master serial mode)
N.C.
N.C.
I
Vsync input
I
Hsync input
I
Video standard input
I
Video standard input
I
Video standard input
O
Reset output
I
Channel Status or Fs Indicator input
Digital GND
I/O power supply (3.3V)
Core power supply (2.5V)
I
Channel Status or Fs Indicator input
I
Channel Status or Fs Indicator input
I
Channel Status or Error Status input
I
Channel Status or Error Status input
I
Channel Status or Error Status input
Digital GND
I
Channel status input (serial)
O
Selection setting output of sub frame 1 or sub frame 2
O
Selection setting of pin function of C0 to CE
Core power supply (2.5V)
I
Same as the SDI_BCK
I/O power supply (3.3V)
Digital GND
I
The 27MHz clock which generated from SDI
2
3
Pin Function
PRA-BD11
3
4
4

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