Motorola MC68340 User Manual page 165

Instruction
ANDI # data , SR
EORI # data , SR
MOVE
MOVEA
MOVEC
MOVES
ORI # data , SR
RESET
RTE
STOP
LPSTOP
BKPT
BGND
CHK
CHK2
ILLEGAL
TRAP
TRAPcc
TRAPV
ANDI # data CCR
EORI # data CCR
MOVE
ORI # data CCR
5-28
Freescale Semiconductor, Inc.
Table 5-11. System Control Operations
Operand
Syntax Operand Size
Privileged
16
16
ea , SR 16
SR, ea 16
USP, An 32
An, USP 32
Rc, Rn 32
Rn, Rc 32
Rn, ea 8, 16, 32
ea , Rn
16
none none
none none
# data 16
# data none
Trap Generating
# data none
none none
ea , Dn 16, 32
ea , Rn 8, 16, 32
none none
# data none
none none
# data 16, 32
none none
Condition Code Register
8
8
ea , CCR 16
CCR, ea 16
8
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Operation
Immediate Data SR SR
Immediate Data SR SR
Source SR
SR Destination
USP An
An USP
Rc Rn
Rn Rc
Rn Destination using DFC
Source using SFC Rn
Immediate Data V SR SR
Assert RESET line
(SP) SR; SP + 2 SP; (SP)
SP; restore stack according to format
Immediate Data SR; STOP
Immediate Data SR; interrupt mask
STOP
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal
instruction.
If background mode enabled, then enter background
mode, else format/vector offset
PC – (SSP); SR – (SSP); (vector)
If Dn < 0 or Dn < (ea), then CHK exception
If Rn < lower bound or Rn > upper bound, then
CHK exception
SSP – 2 SSP; vector offset
SSP – 4 SSP; PC (SSP);
SSP – 2 SSP; SR (SSP);
llegal instruction vector address
SSP – 2 SSP; format/vector offset
SSP – 4 SSP; PC (SSP); SR
vector address PC
If cc true, then TRAP exception
If V set, then overflow TRAP exception
Immediate Data CCR CCR
Immediate Data CCR CCR
Source CCR
CCR Destination
Immediate Data V CCR CCR
PC; SP + 4
EBI;
– (SSP);
PC
(SSP);
PC
(SSP);
(SSP);
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