Timing Example 3-Negative Tails; Example 2—Branch Not Taken; Example 3—Branch Negative Tail - Motorola MC68340 User Manual

1
CLOCK
1 PRE-
BUS
FETCH
CONTROLLER
INSTRUCTION
MOVEQ
CONTROLLER
MOVEQ
EXECUTION
TIME
#7,D1
5.7.2.3 TIMING EXAMPLE 3—NEGATIVE TAILS. This example (see Figure 5-36) shows
how to use negative tail figures for branches and other change-of-flow instructions. In this
example, bus speed is assumed to be four clocks per access. Instruction three is at the
branch destination.
Although the CPU32 has a two-word instruction pipeline, internal delay causes minimum
branch instruction time to be three bus cycles. The negative tail is a reminder that an extra
two clocks are available for prefetching a third word on a fast bus; on a slower bus, there
is no extra time for the third word.
1 2 3
CLOCK
BUS
BRANCH OFFSET
CONTROLLER
INSTRUCTION
MOVEQ
CONTROLLER
EXECUTION
MOVEQ #7,D1
TIME
Figure 5-36. Example 3—Branch Negative Tail
5-96
Freescale Semiconductor, Inc.
2 3 4 5
6
2 PRE-
FETCH
OFFSET
CMP
CALC
CMP
BLE.B NOT TAKEN
D1,D0
Figure 5-35. Example 2—Branch Not Taken
Instructions
MOVEQ
BRA.W
MOVE.L
4 5
6 7 8
OFFSET
TAKEN
CALC
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7 8 9 0 1 2
3 PRE- 4 PRE-
WRITE
FETCH
FOR 4
FETCH
NOT MOVE TO
TAKEN (A0)
MOVE.L D1,(AO)
#7, D1
FARAWAY
D1, D0
9 0 1 2 3
FETCH NEXT
FETCH MOVE.L
INSTRUCTION
BRA.W FARAWAY
4
3
WRITE
FOR 4
4 5 6
7 8 9
PREFETCH
MOVE
TAKEN
TO D0
MOVE.L D1,D0
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